FPGAs are a great solution for prototyping because they offer designers the flexibility to test a design in the application without incurring large NRE charges. Design iterations can be performed using the same FPGA prototype device until the final working solution is attained. However, a completed design often requires a different set of priorities: lower cost, lower power and better performance. Structured ASICs offer a solution to this shift from a prototype emphasis to production design requirements at less risk than a comparable cell-based ASIC implementation. Structured ASICs also offer several key performance advantages over FPGAs, primarily in the areas of power reduction, clock performance and core density.
Due to their programmable nature, FPGAs use a great deal more power than ASICs. The most advanced FPGAs offer users a reasonable amount of logic and memory, and by default an enormous number of transistors are required to support that capacity. Most designs do not use everything available in the FPGA so a large portion of the transistors are active although not used in the functional circuit. This is a constant source of power drain on the completed design. The large amount of programmable logic and memory available on an FPGA also results in a large die size. Programmable interconnects across the FPGA represent a significant portion of the chip and are another constant source of power drain. In routing a design through an FPGA, there is no direct path between any two points requiring a lot of switches to turn on a given path. Using a large number of switches for a given route is a third source of high power use. Finally, FPGA designers cannot use programmable interconnects with clocks. This results in the need for a large clock network across the surface of the die, again using a great deal of power.
On the other hand, a structured ASIC is programmed in the upper levels of the fabrication process to the meet a specific logic function. Logic that is not used in the circuit design is not connected and in many cases can be powered down to further conserve total power usage. ASIC memories that are embedded in structured ASICs as large blocks are also faster and use less power than FPGA memories. Routing is also optimized to the shortest path between two points on the circuit further reducing the amount of power used. Finally, multiple clocks can be used and the circuit timing optimized to find the balance between power and performance. Considering all of these power saving options, it is common for a structured ASIC design to use 20 percent less power than the same design implemented in an FPGA.
Use of a structured ASIC versus an FPGA can also improve clock performance. Unused programmable interconnect is stripped away in the structured ASIC design leaving only that which is needed to make the design functional. Routing is also improved as necessary paths do not need to route through switches and overall clock speeds can be increased dramatically. In cases where structured ASICs need to match the performance of an FPGA, delay elements are introduced to slow the structured ASIC to meet the performance of the FPGA. This difference in core logic and memory speed allows designers the flexibility to do one of two things: either increase the overall performance of the design to levels unattainable by the FPGA, or cost reduce the structured ASIC design by using an older process technology. In the latter case, if a structured ASIC need only match the performance of the FPGA but not exceed it, an ASIC technology one process generation behind the FPGA can be used. For example, if a design is implemented in a Xilinx Virtex-II Pro FPGA, which uses a 1.5V 0.13 m m technology, the structured ASIC replacement can be implemented in a 0.18 m m technology that will still match the timing of the FPGA. As most designers know, implementing a design in an older structured ASIC technology allows for drastically reduced engineering costs since mask costs are increasing at an almost logarithmic rate. One important point to note is that operating voltage could change if designers choose to replace an FPGA with a lower cost structured ASIC process technology. If the FPGA design is implemented in a 1.5V product and a designer wants to replace the design with an older technology structured ASIC, the ASIC solution will likely be in a 1.8V process. However, with foresight on the designer’s part the board layout can accommodate this and the total system cost will be further reduced.
Figure 1: Core limited die size typical of a FPGA
Another key advantage that structured ASICs have over FPGAs is core density. In order to maintain their programmability, FPGAs carry a great deal of transistor overhead both for the core logic of the part as well as the memories. Depending on the manufacturer of the structured ASIC, core logic density is seven to 10 times greater than that of an FPGA in a comparable technology. A design that is prototyped in an FPGA and later retargeted to a structured ASIC uses significantly less silicon in the structured ASIC, meaning that the finished design as implemented will have a much lower cost. Most FPGAs are core limited, i.e. the core area of the silicon is the limiting factor in die size.
(Figure 1) An equivalent structured ASIC is typically pad limited, i.e. the pad ring around the silicon is the limiting factor in die size. (Figure 2) Hence, in order to reduce the final cost of the design as implemented in a structured ASIC it is prudent to reduce the total number of I/O used to the point that the I/O are no longer the limiting factor in the size of the structured ASIC die. The smaller structured ASIC die allows users to lower their production design cost to a fraction of the FPGA cost, typically by a factor of five to ten times.
|Figure 2: Pad limited die size typical of a structured ASIC
It is clear that major cost and power reductions can be obtained for most designs prototyped in an FPGA while maintaining or improving design performance when moved to a structured ASIC. There are generally two reasons to stay in an FPGA. One, the design is slated to continue changing throughout its life (requiring continued reprogrammability), or two, production volumes are so low that investing in a structured ASIC development does not make sense. In the former case it is pretty clear that the FPGA is the preferred solution. However, in the latter case it is still a good idea to contact a structured ASIC vendor to make the cost/volume tradeoff analysis since structured ASICs have a surprisingly low cost of entry. With ASIC-like performance at a fraction of the cost, it is no surprise that structured ASICs are gaining momentum as a production replacement of FPGAs.
About the Author
Dave Larson currently serves as AMI Semiconductor’s (NASDAQ: AMIS) strategic marketing manager for the Structured Digital Products business unit. His responsibilities include market research and segmentation, competitor analysis, business and product planning and revenue forecasting for the units target markets, including communications, computing, electronic data processing and military/aerospace.