There is a radical shift in the beliefs about high speed serial feasibility as it moves beyond 3 Gbps on up to 10 Gbps. In a matter of few short years, the industry has gone from saying “impossible” to the concept of 10 Gbps with existing CMOS NRZ signaling to today, where all the required productized elements are in place for delivering manufacturable systems operational anywhere from 2.5 to 10Gbps. These components include: off the shelf transceivers, backplanes and connectors.  The reason for this shift has been a concerted, partnered effort by all parties including semiconductor vendors, backplane, connector manufacturers and signal … Read More → "Making the Jump to 10G"

A little over a year ago, when we wrote our last feature on high-speed serial I/O, you might have felt safe. You could read the article with a secure fascination, isolated from personal involvement with the risks of the technology and amused at the lengths to which those telecom types would go in order to cram more bandwidth onto the backplane – safe in the knowledge that your own precisely-tuned parallel busses were merrily megabitting away on your little low-tech circuit boards. Now, the subject may feel a bit more uncomfortable. With standards like PCI Express gaining increasing momentum, … Read More → "Breakthrough Bandwidth"

FPGA designers are typically working with prototype designs without much synthesis history, so on the first pass of the design they will not have developed a set of false path and multi-cycle path constraints. FishTail’s Focus tool can generate false path and multi-cycle path timing exceptions for the FPGA designer before the first synthesis run. These timing exceptions have the ability to improve FPGA QoR by relaxing constraints on the timing paths of the design and potentially allow the FPGA to run faster. In this paper we have studied the impact of timing exceptions on nine designs … Read More → "The Impact of Timing Exceptions on FPGA Performance"

Most of us picked up HDL design the way we discover a new city. We land at the airport, and a taxicab drops us off at some arbitrary location – a hotel perhaps. From that point, we branch out in an ad-hoc manner, discovering things mostly by accident, and gradually building a mental picture of the place for ourselves. Different people may develop entirely differing views of a place depending on when and how they landed there and how their luck went in this semi-random discovery process. Much of what you discover first is based on what you were trying … Read More → "Simulator Savvy"

Configuring and implementing an FPGA-based embedded system is not an easy task. Connecting various blocks of discrete intellectual property (IP) in a system using an FPGA, and making them all work together, continues to be difficult and time-consuming. Instead of designing a system themselves, engineers need a solution that can be quickly configured to closely match their design’s required functionality, for the lowest possible cost. A solution that combines FPGAs with a hardware-based system-on-module (SOM) approach makes this possible.

One of the major benefits of using an FPGA-based embedded system is the ability to re-use a … Read More → "FPGA-based System-on-Module Approach Cuts Time to Market, Avoids Obsolescence"

Nick Martin is not bound by high-tech tradition. If he were traditional, he’d have a PhD from Berkeley, UC Irvine, or MIT. If he were traditional, his COO would be an MBA from Stanford and Altium would be another venture-funded EDA company in a high-tech corridor like Silicon Valley, Research Triangle, or Boulder. If he were traditional, Altium’s tools would be 80% functional, they’d have no sales or distribution channel, and they’d be looking to be acquired by one of the three major EDA companies.

Instead, Nick is founder and … Read More → "Nick Martin"

Field-programmable gate arrays (FPGAs) have a well-established position in every systems engineer’s toolbox. Taking advantage of their flexibility, engineers have used FPGAs for many years to rapidly prototype systems or in low-volume pre-production applications. When the communications- and network-driven Internet bubble took off at the turn of the millennium, demand skyrocketed for FPGAs in higher gate densities at any cost. Since then, however, FPGA requirements have changed dramatically. Today, as companies increasingly focus on the bottom line, engineers look for silicon solutions that offer both low unit and low total system cost. While ASICs have traditionally offered … Read More → "Considering the Total Cost of FPGAs"

If the value of structured ASIC as a gap-filler between programmable logic and cell-based ASIC is still in question, there are at least two companies on opposite sides of that gap where a decision has clearly been made. Both LSI Logic and Altera unveiled new families this week aimed at attacking this new and potentially lucrative segment of the silicon landscape. Interestingly, both companies’ involvement in structured ASIC can be viewed as a defensive move. As a leading supplier of cell-based ASICs, LSI shored up its defenses against attack from the other side of the FPGA/ASIC … Read More → "Structured ASIC Starting Line"

Could this be the iPod of FPGA families? Has Actel created the happy little “chip that could” to take on the SRAM-dominated titans of the low-cost FPGA battlefield? Will ProASIC3 Development boards be proudly displayed on the desks of any development team that wants the nice, clean look and feel of a secure, single-chip, ready-at-power-up, low-power, no-hassle solution to their high-volume, middle-of-the-technological-road design problem?

Like other programmable logic vendors, Actel has noticed that cell-based ASICs are becoming an increasingly specialized solution for high-volume electronics products. Only the best-funded, most risk-immune, highest-volume-and-performance applications can realistically justify … Read More → "Flash News Flash"

Designing an efficient processor-based system architecture with overall system performance optimized for a specific application is not trivial, requiring skills and technology similar to those employed by supercomputer designers. Accomplishing this feat requires new tools and methodologies to augment the EDA flow for both traditional ASIC design and the new class of programmable SoCs, e.g., FPGAs. Architectures and performance must be verified early in the design cycle; the designer cannot wait until RTL development to discover their architecture does not support their system requirements.

Problems to Solve

Current processor tools have not kept up … Read More → "Accelerating Processor-based Systems"