feature article
Subscribe Now

Are These Guys Dense, or What?

Newest Class of FPGAs Makes Dense Cool

Context can drastically impact the meaning of a simple word. If you’re walking down the street minding your own business, you might find yourself feeling more than a little bit offended if someone calls you dense. You may even experience a brief but painful flashback to that dreaded walk through the gauntlet of cool kids lining the halls in school, hearing any number of rude, if inaccurate, comments (after all, who’s calling who dense?) thrown with casual abandon in your direction. Now, change the circumstance. You’re at a tradeshow, heading back to a demo station in your company’s booth. You find yourself facing another gauntlet of sorts, but this time it’s lined with people wanting to see your latest product and admiring its components, including, by the way, some “wicked dense FPGAs.” Suddenly, dense is cool.

This new class of FPGAs has just two members: Stratix II from Altera, and Virtex-4 from Xilinx. Although they both carry on their family names, following Stratix and Virtex-2 Pro, respectively, these 90nm device families deliver much more than standard generational improvements over their 130nm forefathers.

As expected, both device families offer higher density, lower cost per gate, and better performance. But before the vendors could dazzle us with all the trappings of their new offerings, they had to face the most daunting (and perhaps most anticipated) hurdle in making a move to 90nm: power. In an FPGA, power is broken down into two components: static and dynamic. It used to be that dynamic power (i.e., the power it takes to perform functions when the chip is running) was the big eater. But every time process geometry gets smaller, gates get thinner. Thinner gates leak more current (upping the static power consumption). There was a concern that if nothing was done to stop the trend, leakage current could all but take over as the power hog and potentially threaten the long-term viability of high-density FPGAs.

Both vendors successfully overcame the power issue, albeit in completely different ways. Xilinx tackled static power, using a new leakage-reducing “triple-oxide” technology where transistors can have one of three different oxide widths, depending on the speed demands they’re facing. Altera had started their power reduction strategy at 130nm with an all-copper process on 300mm wafers. At 90nm, they incorporated low-k dielectric material and actually improved power dissipation. Given the different approaches that Altera and Xilinx have taken to tackle power at 90nm, it will be interesting to see how each continues on the next process node.

Process improvements may have addressed power, but the next challenge was performance. “On its own, the move from 130nm to 90nm delivered a performance improvement of only 15-30% over our Virtex-2 Pro device family, so we needed to make fundamental changes to the architecture,” said Per Holmberg, Senior Director of Virtex Marketing at Xilinx. Xilinx leveraged the flexibility of flip-chip technology to create their Advanced Silicon Modular Block (ASMBL) architecture, which enables them to deliver three domain-optimized platforms that offer designers varying mixtures of capabilities at every price point. The base platform (called LX) is fairly generic, while the other two are intended for specific classes of design. SX focuses on DSP, and FX is targeted at embedded processing and high-speed serial I/O.

The architecture revolution was happening in parallel at Altera, where they created a new logic structure called Adaptive Logic Module (ALM) for Stratix II. ALMs can be flexibly repartitioned into various configurations for input sharing, enabling super efficiency for narrow logic elements and high performance for wide ones. According to Altera, compared to their previous LUT4-based architecture, the ALM delivers more logic capacity in less space, better performance, and much higher adaptability for applications.

Both device families have shiny new architectures designed to optimize performance, and both deliver significantly more hard IP, features, capabilities, and flexibility than their predecessors. Although they approached the challenge in very different ways, both FPGA vendors have ended the 90nm challenge at almost exactly the same point. It’s as though Altera started at “A” and Xilinx started at, well, “X” and they both ended at “M.” Density, performance, and power claims aside, it’s likely that the feature mix and toolsets will most often be key deciding factors in selecting a family.

If You Build it, They Will Come. Right?

They’re cool. They’re capable. They’re so flexible they could have an act in Cirque du Soliel. Now, where do they fit? The first impression you might have upon hearing all these new features and benefits is that these device families open the doors to huge new markets. Despite significant cost gains made by this generation of devices, cost is still guarding the door. It turns out that the real door openers for the FPGA vendors are the low-cost FPGA families – Xilinx’s Spartan-3 and Altera’s Cyclone II. These FPGAs are taking high-volume markets like consumer and automotive by storm with densities that approach first-generation Virtex and Stratix offerings. But that’s another story.

So, why would you pay more for these high-end devices? Features, baby, and lots of ’em. You get more logic, a lot more DSP blocks, high-speed serial I/O, tons more memory, more embedded processor capabilities, and just more I/O in general (you can never be too rich or have too much I/O).

Traditionally, high-end FPGAs have had two primary footholds. The first is design teams using FPGAs for prototyping. For these customers, the 90nm devices get them more equivalent gates and more speed, resulting in incremental capability improvements. The second is designers using FPGAs in production. These guys are the real envelope pushers. They need the most density and performance that you can throw at them, but they also need the flexibility and rapid time-to-market of a programmable device. They don’t mind the comparatively high unit cost of these devices. That’s a tradeoff they’re more than willing to make. These are the high-density “heartland” FPGA customers, coming mostly from markets like communications and networking.

Both Xilinx and Altera say that the high-density devices have helped deepen their reach into their existing customer base, moving them into new parts of the design. For example, a customer could be using an ASIC or ASSP for the part of the design that they’re sure of, and an FPGA for the part that’s still in flux. The size and flexibility of the Virtex-4 and Stratix II device families make them a viable choice for this type of design, creating more options for what can be put on the device and allowing designers to bring more of their system onto the FPGA.

A prime example of the trend toward increased FPGA integration is in the DSP realm, where designers who have not worked with FPGAs in the past are seeing new possibilities for both flexibility and performance. The two keys to DSP success are the ability to parallelize arithmetic functions, particularly multiplication, and the tool flow to simplify the hardware design task for DSP designers. Both FPGA vendors offer solutions specific to DSP users, with dedicated hardware blocks that can dramatically accelerate DSP performance and specialized design tools for DSP design. Each FPGA vendor offers devices with hundreds of DSP blocks that include 18×18 multipliers, offering the potential for dramatic DSP acceleration when compared to traditional DSP processors.

Another trend is in embedded design. Xilinx’s Virtex-4 FX product includes an embedded PowerPC and Ethernet MAC, as well as their RocketIO multi-gigabit serial transceivers. In addition to the hard-core PowerPC, Xilinx has two soft-core processors (the 8-bit PicoBlaze and the 32-bit MicroBlaze). Altera’s Stratix II emphasizes flexibility with their established Nios and Nios II 32-bit soft cores combined with the versatility of their SOPC builder and its rich selection of embedded peripherals and IP. As these device families continue to strengthen their embedded capabilities, they become increasingly viable for the embedded design community at large.

Now back to those pesky, well-guarded new market doors. Although the high-density devices don’t open them on their own, they have carved an important niche for themselves in higher-volume applications when paired with some innovative cost-reduction techniques. Altera’s innovation is a structured ASIC solution called HardCopy. If you’re starting with a Stratix II FPGA, you can move it into HardCopy to reduce your cost per device and get the benefits of a structured ASIC (faster, lower power, etc.). “By combining Stratix II with HardCopy, customers can get to volume production much faster, and react to changes with a lower NRE,” said Paul Ekas, Senior Marketing Manager for high-density FPGAs at Altera.

Xilinx’s answer to the cost conundrum is called EasyPath. EasyPath keeps cost down by design-specific testing of Virtex-4 devices. Essentially, you keep the convenience, power, and features of the FPGA but reduce your cost by giving up some of the reprogramming flexibility.

Addressing the Design Challenge

With all of the functionality and flexibility of these high-density devices comes a new level of design challenge, and according to the EDA vendors, it’s not just the size of the designs that matters. “By adding more system functionality, designers have a reprogrammable platform that they can put more memory into, more fixed IP blocks, processors, and more,” said Juergen Jaeger, Director of Channel Marketing at Mentor Graphics. “That brings up challenges that have more to do with assembling the designs.”

As ASIC-grade challenges like team design, design cycle predictability, and verification creep into the FPGA world, the EDA vendors can help with the transition. “Design size, complexity, clock speeds, and IP requirements are making these FPGA devices very similar to ASIC designs,” said Gal Hasson, Director of Marketing, RTL Synthesis, at Synopsys. “Putting ASIC designs on FPGAs requires ASIC-grade tools.”

In addition, the EDA vendors have their eye on designers migrating to high-density FPGAs for their new capabilities, particularly in DSP. “DSP applications are really starting to gain momentum,” said Jeff Garrison, Director of Marketing at Synplicity. “It’s looking like the primary inroad for the big devices, and we’ve added specific tools and functionality tailored to this area.”

In other words, there’s no shortage of opportunities when it comes to design challenges for high-density FPGAs, and the EDA vendors are working hard to stay ahead of the changing landscape to help customers get the most of every new feature.

So, dense is cool. And as the vendors continue to pile on features, performance enhancements, and cost-saving innovations, it’s only going to get cooler.

Leave a Reply

featured blogs
Jul 20, 2024
If you are looking for great technology-related reads, here are some offerings that I cannot recommend highly enough....

featured video

Larsen & Toubro Builds Data Centers with Effective Cooling Using Cadence Reality DC Design

Sponsored by Cadence Design Systems

Larsen & Toubro built the world’s largest FIFA stadium in Qatar, the world’s tallest statue, and one of the world’s most sophisticated cricket stadiums. Their latest business venture? Designing data centers. Since IT equipment in data centers generates a lot of heat, it’s important to have an efficient and effective cooling system. Learn why, Larsen & Toubro use Cadence Reality DC Design Software for simulation and analysis of the cooling system.

Click here for more information about Cadence Multiphysics System Analysis

featured paper

Navigating design challenges: block/chip design-stage verification

Sponsored by Siemens Digital Industries Software

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop verification iterations, saving time, improving accuracy, and dramatically boosting productivity.

Click here to read more

featured chalk talk

Exploring the Potential of 5G in Both Public and Private Networks – Advantech and Mouser
Sponsored by Mouser Electronics and Advantech
In this episode of Chalk Talk, Amelia Dalton and Andrew Chen from Advantech investigate how we can revolutionize connectivity with 5G in public and private networks. They explore the role that 5G plays in autonomous vehicles, smart traffic systems, and public safety infrastructure and the solutions that Advantech offers in this arena.
Apr 1, 2024