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IP for Increased Productivity

The preparation starts weeks in advance. Whole grains are stone-ground – the resulting flour combined with honey extracted from backyard beehives over a period of months. The dough is then pressed and baked on hand-forged pans in wood-fired ovens until a fine golden crust appears that can be crushed into flakes of exactly the right consistency. After cooling, the flakes are poured into handmade pottery bowls, fired the previous week after being slung from native clay dug from the local riverbed. Finally, right before breakfast, milk from cows raised on grain grown in your own field is poured over the mixture. Making your own breakfast cereal can be a long and arduous task. But when you’re done, all the weeks of preparation, expert handling, and expense give you something that resembles, well, the breakfast cereal you can buy in a box at the local supermarket.

How do you decide what to buy and what to develop yourself? The best dividing line is differentiation. Any part of your design that does not differentiate your product from your competitor’s should be fair game for IP. The most common blocks that fall into this category are those that are standards-based. You’re probably not going to beat your competition by having a better USB, Ethernet, or PCI interface than theirs. Likewise, as long as your DDR or DDR2 memory interface works reliably, it probably won’t be the reason customers buy or don’t buy your product. Engineering time you invest in re-inventing these important functions is time you could have spent making your product better, or time you could have been on the market capturing additional market share.

Worse yet, unless you’re an expert at the particular standard you’re tackling, you just might end up with a marginal implementation that will mar your product, or extra design time validating and de-bugging a block you never should have designed in the first place. At best, you’ll end up with an implementation comparable to commercially available IP, but with far less testing and validation behind it.

The IP core movement started with attempts at design re-use within large companies. “While there was much talk about re-use, few design managers were willing to extend their project deadlines in order to package up IP for the ‘public good’,” says Yankin Tanurhan, senior director of IP and applications at Actel. “The idea just didn’t go anywhere. Even though people tried to develop tools to make the process easier, it didn’t help much.” Commercial IP vendors started to spring up everywhere with wild expectations of capturing huge returns on an exploding new market, but quality concerns quickly doused the entrepreneurial fires and put prospective customers on notice.

Actel was one of the first to feel the quality pressure from customers, as many of their devices have traditionally been used in high-reliability applications like space-bound devices and avionics. “Actel is lucky having driver-customers who are extremely quality conscious like space, nuclear reactors, and automotive,” Tanurhan continues. “They moved Actel to an early understanding of the quality side of IP, and taught us to deliver cores in a higher quality way.”

In the past, obtaining third-party commercial IP was a lot like trying to buy a Rolex on a street corner. Lots of people were selling things that looked good enough on casual inspection, but your intuition told you that under the hood you might not be getting what you paid for, and follow-on support would be difficult to find. “Lots of people got burned badly by the early IP market, even by suppliers with good reputations,” says Tanurhan. “It was like cutting parts for your car at a junkyard. You knew the part you were getting was probably broken and you just hoped that you’d be able to make it work somehow before your Dad found out.” Fortunately, the IP industry has matured significantly in the past few years. Driven by the ASIC IP market, lots of high-quality, well-supported offerings have made their way into the FPGA domain.

Synopsys, a leading supplier of ASIC IP, has almost backed into the FPGA market because of the strong demand for ASIC IP to be compatible with FPGA-based design verification. Design teams using commercial IP blocks wanted to be able to use the same IP in their FPGA-based prototype that they used in the final production version. “Synopsys IP customers are usually targeting production volume ASICs, but nearly all of them use FPGAs for prototyping,” says Phil Dworsky, Synopsys’s Director of IP Applications and Marketing. “We provide IP that can target both environments without having to re-design. We architect our cores so they run at speed in FPGA. We also use FPGA implementations of our cores during certification.” Normally, if a core will operate at speed in an FPGA-based implementation, there is no problem with an ASIC version, as FPGAs have considerably less timing flexibility than ASICs.

How do you know what amount of verification has been done, though? “You need to look at the vendor as well as the IP itself,” Dworsky continues. “You want to see the whites of the designer’s eyes and understand their approach to quality and verification. Look specifically at their verification plan and know the status of their verification of your particular block. Building a relationship with a trusted IP vendor takes some investment, and it’s best to amortize that cost across a large amount of IP.” Many companies are turning to a few trusted suppliers for their IP portfolio rather than tackling each IP acquisition separately. This allows them to leverage master legal and purchasing agreements as well as verification process reviews over a large number of projects rather than bearing the cost on just one or two.

Another consideration in choosing IP for FPGA-based ASIC prototyping is licensing. The “free” IP you get from your FPGA vendor may make quick work of the FPGA implementation, but you should be sure that those blocks are legally available for later ASIC use, and know the cost before you go casually dropping them into your design. Altera recognized this issue some time ago, and they license most of their cores for ASIC use for an additional cost. “Altera has always licensed MegaCore IP for 3 rd party ASIC use,” says Justin Cowling, Altera’s director of IP and technology marketing. “We want to support the prototyping business. The biggest challenges aren’t in synthesizable IP, but in hard IP like DDR I/O and SerDes in FPGAs. Synthesis tools are so good right now that for synthesizable IP, you’re better off to take FPGA IP and move from there to ASIC. Trying to move ASIC-based IP back to into FPGAs is where you can run into problems.”

When FPGAs are your final production vehicle, the IP question is often even more important. Design teams tend to choose FPGAs because of their flexibility and time-to-market advantages. Spending a few extra weeks developing what’s readily available in IP cores deflates those advantages considerably. In addition to the extra time designing these blocks yourself, you extend your debug and verification cycle and increase your overall project risk. Increasingly, design teams are taking advantage of the availability of cores for as many standard functions as possible. “One sign that the IP market for FPGAs is maturing,” Cowling continues, “is that many of our customers are now starting to tell us clearly that they will always use an IP core if one exists for the function they need. A few years ago, the answer was much more varied and inconclusive.”

Altera’s experience with IP customers has revealed some consistent themes in what design teams want and expect with commercial IP. First, designers want complete and accurate documentation. There is a wide discrepancy among IP vendors in the amount and quality of documentation supplied with a core. Some are robust and complete, while others don’t even contain timing diagrams. When you look at IP cores, be sure to check out the documentation in advance so you’ll know whether it contains what you’ll need to plumb it into the rest of your circuit.

Second, design teams want simple licensing agreements that don’t require a lengthy review by their legal department. Since time-to-market is one of the key advantages of FPGA-based implementation, it doesn’t make sense to delay your product for several weeks of legal changes to licensing agreements. More often today, IP vendors are adopting standardized “click-through” licensing agreements that simplify the process and eliminate the legal department from at least one part of your design cycle.

Finally, IP cores are complex and will almost always contain bugs. While designers don’t expect IP to always be bug-free, they do expect IP vendors to be forthcoming with errata. It can be very frustrating to spend weeks hunting down a problem with your design, finally trace it to an IP block, contact the IP vendor and get a response like “Oh yes, we know about that bug and you can download the fix here…” If the vendor supplies an accurate list of known problems and limitations, it can save you a lot of time and frustration in debug.

While FPGA vendors are happy to support the use of their IP in later ASIC-based cost reductions, don’t expect them to let you move IP to a competing FPGA vendor. As we discussed last year in our “Sticky Business” article, inexpensive IP is one way for FPGA vendors to lock you into their technology, making design migration difficult. On the other hand, if you’re sure of your FPGA decision, vendor-supplied IP can deliver great productivity improvement, risk mitigation, and incredible value for your investment.

Some of the hottest cores on the market today are those that turn FPGAs into system-on-chip platforms. These cores, including soft- and hard-core processors, peripherals, and interfaces, are powerful aids in creating FPGA-based systems on minimal schedules. Altera has seen great success with their Nios and Nios II cores, and Xilinx has just introduced a new version of its popular MicroBlaze soft-core processor, boasting better performance than its predecessor, with more flexibility and a new floating-point unit for high-performance math acceleration. As more and more of these high-value cores find their way into FPGA portfolios, the advantages of FPGAs as system design platforms will continue to increase.

Vendors invest significant engineering resources in creating and verifying these cores, and they plan to recoup that investment in silicon sales. It is no longer sufficient to compare FPGA offerings based on the devices alone. Your complete picture has to include the availability of IP cores that will get your design done quickly, smoothly, and with minimal risk and cost. If you take IP into consideration in your decision making process early, before you commit to a particular implementation technology, you can save yourself a lot of headache down the line.

If you’re uncertain even of what FPGA vendor you’ll be using, or if you think your design might be migrated over a number of years as FPGA technology changes, consider vendor-neutral FPGA IP offered by companies like Altium. “Our approach is to make FPGA design easy and approachable,” says Nick Martin, Altium founder and CEO. “We see an important trend in migrating complexity from board-based systems into systems centered around programmable devices like FPGAs. By using vendor-independent IP and tools, you maximize the flexibility advantages that FPGAs offer and create designs that are easier to migrate in the future as FPGA technologies change and evolve.”

Whatever IP you choose today, it will probably be more efficient than designing the same thing yourself. The “Not Invented Here” syndrome is hard to conquer, but leaving the renaissance-designer attitude behind can pay dividends in both productivity and profitability. You’ll get your project finished faster, with higher quality and less frustration. Then you’ll have plenty of time left over to work on that new cornflakes recipe…

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