In most markets, there exist a set of de-facto rules. Sport-utility vehicles have bad fuel economy. Economy cars have limited cargo space. FPGAs use too much power. ASICs have staggering non-recurring engineering (NRE) costs. Generally, the players play by those rules, and the consumer enters every buying decision with a pre-defined understanding of the tradeoffs those rules imply and which basic option favors their situation. The final choice is then decided by a comparison of the less-critical factors that differentiate the products in each area. Once a design team has decided to go with a zero-NRE solution, for example, they typically find themselves comparing various FPGA offerings to find the one that best fits their needs.
Occasionally, however, someone breaks the rules. What if you could get an ASIC with near zero NRE? Would you still be locked into an FPGA solution? What if a structured ASIC offered you some degree of reprogrammability, or if you could vary the design on a small lot basis? Your decision approach, and even your entire design, might shift dramatically.
eASIC has announced its new FlexASIC family of structured ASIC devices that break the established rules. FlexASIC offers density, performance, and power consumption that come close to cell-based ASIC, with flexibility, NRE, and risk avoidance much closer to the FPGA end of the spectrum. This is accomplished by using an innovative architecture that combines FPGA-like look up table (LUT) cells connected by metal routing that is customized by a single via layer. This single via layer can be e-beam programmed for small production runs, or mask programmed for higher volumes.
An additional advantage of the e-beam programming approach is the ability to easily segment wafers, putting multiple design variants on a single wafer. This eliminates minimum volume requirements and ultimately lowers unit costs as a single production lot can be shared across many designs. While e-beam has suffered a somewhat dubious reputation in the past for impractical levels of performance, eASIC points out that their use of e-beam is comparatively fast because only a single via layer is being customized. When it comes time to go to production, no requalification is necessary because the mask-customized version will be identical to the e-beam version.
From a security perspective, FlexASIC also offers the best of both worlds. The via-based routing makes reverse-engineering of the routing fabric extremely difficult, and because the logic is bitstream programmed, the device itself does not contain the entire design until runtime. Potential thieves would have to recreate both elements to have a viable copy of the design.
FlexASIC via customization scheme.
Architecturally, FlexASIC is perhaps closest to Altera’s HardCopy in that it uses metal-to-metal connections between LUT structures, but FlexASIC is actually closer to an FPGA in that the LUTs are bitstream programmed where HardCopy’s logic is all mask programmed. They key to the unique value of FlexASIC is the single-layer programming. Because programming is accomplished solely via vias, and because those vias can even be e-beam programmed, eASIC is able to offer a near-zero NRE customization with very fast turnaround. From the system design perspective, FlexASIC comes very close to FPGAs in turnaround, NRE, and risk, where it comes out virtually identical to structured ASIC in performance, price, and power consumption.
From a density perspective, FlexASIC most closely overlaps high-end FPGA families with a density range from 250K to 3M “ASIC gates”. Since we’re dealing with a LUT-based architecture, however, density requires a bit more explanation. The family contains from 16K to 192K “eCells”. Each eCell is structurally similar to a Xilinx slice or an Altera ALM. The eCells contain two almost-four-input LUTs (meaning three-input LUTs with one input of the LUT occupied by a two-input NAND.) If we just compare LUT counts (and your LUT mileage may vary considerably depending on factors like synthesis and layout efficiency, the topology of your design, and the phase of the moon) the largest FlexASIC has something like double the LUT count of today’s largest 90nm FPGAs.
FlexASIC also includes from zero to about 2.8 megabits of block RAM, from one to eight PLLs, and from 118 to 744 user I/O pins. As in many FPGAs, the eCells can also be used as distributed RAM, adding to the memory capacity and performance when needed. The bitstream programmability of eCells also permits them to be used to create a virtual PLD within your design. Using this approach, parts of the design can be made to be field-customizable by reprogramming a PLD section.
When it comes to verification, FlexASIC is most like FPGAs and structured ASICs. Tedious tasks like layout verification are all completed ahead of time as part of the base design so you don’t have to worry about them, the risk they carry, or the expensive tools they require. FlexASIC has full BIST for logic and memories, so testing via conventional ASIC methods is possible.
FlexASIC is fabricated on 130nm technology, but eASIC claims that architectural advantages still give significant price, power, and performance advantages over 90nm FPGAs. While specific data is not yet available, eASIC claims that performance will be in the range of double that of FPGA, cost will be less than one-third, and total power will be more than an order of magnitude better. Given the metal-to-metal routing scheme, these claims seem reasonable enough.
On the tool side, the flow most closely resembles the structured ASIC flow. System-level design is completed using any conventional tools, and logic synthesis can be done either with Magma or Synopsys tools. With the Magma flow, physical optimization is also included. eASIC’s proprietary tools are used for the highly-specialized and unique style of layout required for FlexASIC’s single-via layer customization. The primary outputs of the design process are a via mask for layout customization and a bitstream for logic/LUT customization.
eASIC is partnering with Flextronics Semiconductor and Magma Design Automation, with Flextronics providing manufacturing services and Magma offering design tool support. The FlexASIC devices will be offered by both eASIC and Flextronics semiconductor. Prototype silicon is slated for availability in Q3 2005 with production silicon in Q4. Several beta customers are in design and tape-out with the technology today.
As would be the case with any innovative, fledgling technology, FlexASIC lacks the robust infrastructure of tools, support and IP that might be typical of a well-established FPGA family. The benefits are compelling, however, and if the technology gets traction in design-ins, look for the infrastructure to mature rapidly. The new architecture puts considerable additional pressure on low-end ASIC, high-end FPGA, and the entire structured ASIC market. As with any time a rule is changed, watch for the various competitors to respond: structured ASIC vendors by working to reduce NRE and turnaround time requirements, FPGA vendors by leveraging hard-IP based features and infrastructure like DSP blocks, embedded processors, and the tool and IP ecosystem that surrounds them.