Over the past few years, as FPGA devices have increased in density, speed, and started embedding dedicated memory, multiplier blocks, high performance intellectual property (IP), PLLs, and high-speed SERDES, they have become a viable alternative to implement complex designs and applications that traditionally targeted ASIC or ASSP-based designs . This trend however is stressing the limits of traditional FPGA static timing analysis tools and designer productivity is affected.

To meet market requirements and achieve target performance, FPGA design engineers are adopting new design styles and complex clocking schemes (i.e. clock multiplexing in 10M, 100M, 1G … Read More → "Complex ASIC Timing Verification Converges with FPGA-Based Designs"

In my book, ESL is a serious contender for the title of “worst technical term of the decade.” As we’ve discussed before, the ESL label was possibly created by Dataquest in an attempt to create a category that could hold all of the EDA products that didn’t fit cleanly into any of the previously established tool categories. As such, ESL turned into more of a “bucket” than a “category” as it snowballed down the mountain of misfit design software, accumulating technologies such as transaction-level simulation tools, graphical block-based design environments, high level language modeling, behavioral … Read More → "Catapult Levels Up"

Introduction

Ever since hardware description languages (HDLs) were first put into use to specify electronic designs, designers have recycled code. New insights into the use of these HDLs for design are gained by copying and modifying – with the requisite permissions of course – existing examples. By placing that code into the new designs, everybody saves time since designers do not needlessly re-invent an existing block of code. Someone spent significant time and energy to design that code block and other designers rightfully want to leverage that … Read More → "Should You Reuse RTL?"

In the good old days, (those would be the EARLY 2000s) digital signal processing (DSP) was a well-behaved wild animal. It stayed outside in the pasture, grazed off the land, and never harmed the house pets. DSP didn’t disturb the neighbors and didn’t bite unless provoked. If we had a big, complex system, we often hired a specialist, a kind-of DSP whisperer, to handle the care and feeding of our little DSP. He knew all sorts of tricks and techniques for training and taming the little fellows. He spoke MATLAB. He was fluent in DSP … Read More → "Domesticating DSP"

The commercial off-the-shelf (COTS) electronics initiative of the mid-1990s occurred for two key reasons. First, acquiring customized components that could withstand harsh military environments came at a cost premium. Second, highly desirable leading-edge technologies, driven by larger market forces, were being developed for commercial applications. For these reasons, the U.S. government mandated that military contractors begin using a COTS approach, not only to reduce costs, but also to take advantage of emerging technologies.

COTS is based on the premise that military electronics programs could adopt or adapt commercially available components, boards, and systems, … Read More → "Going Beyond COTS Strengthens Mil/Aero PLD Applications"

Everyone knows the ECO. It is a classic case of an acronym acting as a euphemism. Reducing a problematic situation to an established process represented by a simple trio of letters diverts attention from the underlying blunder. “Have Susan process Charlie’s ECO before we bring up that final prototype” sounds much, much more palatable than “Thanks to Charlie’s monumental screwup, Susan will have to attach a big red jumper wire that will now gleam like a beacon of stupidity from the back of the board on every one of our first million units.”

As long … Read More → "Time for a Change"