At first, high speed serial I/O was a checkbox item in FPGAs – either you had it or you didn’t. FPGA vendors bolted transceivers onto their devices, fired off some press releases, and let the games begin. As the race heated up, the competition became one of speed and versatility. FPGA transceiver complexity exploded as vendors vied to lay claim to the most standards and protocols supported, the highest bit rates, the lowest jitter, the highest jitter tolerance, and just about any other specification where a superlative could be claimed.
Of course, the more you try to do everything at once, the less likely you are to do anything well. As transceivers grew in complexity, compromises had to be made in areas like area, power consumption, and yield. Unlike ASIC- and structured-ASIC-based SerDes, transceivers could not be optimized for any particular speed or protocol. The transceiver was fabricated before the application was known, so FPGA-based SerDes transceivers became the Swiss Army knives of serial I/O.
Imagine, however, that you’re shipping something like a Swiss Army knife, and you’re having trouble getting something like the fingernail clipper attachment to work properly. Even though most of your customers don’t care much about that feature, you’re faced with a dilemma – you can’t ship your product with a known defect. In semiconductor terms, you’re faced with two choices – both of them bad. You can ship only those units where the clippers actually work, raising the cost for everyone. You could also try shipping the units with a disclaimer about the clipper functionality. Either way, your product becomes the victim of its own versatility.
Over the past year, we’ve been seeing the first major backlash against the do-all, end-all transceiver. Starting with Altera’s Stratix II GX announcement, we saw for the first time a vendor who backed away from the temptation to go for superlatives over sensibility. Altera shipped their new family with a lower speed range than that already claimed by archrival Xilinx. In the tit-for-tat titanic marketing struggle between the two feuding FPGA vendors, it was an almost unthinkable move, but it paid off. Altera was able to build transceivers that were reliable and efficient at the target speeds of most of their customers, and they probably saved a bundle in the process.
More recently, Lattice Semiconductor followed that philosophy even further, announcing a low-cost FPGA family with embedded SerDes, targeted primarily at two of the most popular protocols – PCI Express and gigabit Ethernet. Lattice reasoned that there were market segments that weren’t able to pony up the big bucks for a high-end FPGA, but that still needed SerDes capabilities.
This week, the trend continues as Xilinx launches their latest 65nm Virtex-5 family, Virtex-5 LXT. Following the diversification trend they started with Virtex-4, Virtex-5 has even more flavors available. In addition to Virtex-4’s logic-heavy LX, the DSP-dominant SX, and the PowerPC-packed FX (which also is the SerDes platform), Virtex-5 is adding a new version “LXT” which is the LX device, but with added SerDes transceivers. Reasoning that not every application of SerDes would also need all of the features of FX (e.g., PowerPC processors and the fastest transceivers), Xilinx decided to drop more mainstream transceivers into the base Virtex-5 family.
Still stinging from last year’s painful launch of the Virtex-4 FX family, Xilinx has modified their approach significantly. First, they are launching their new SerDes family in a much less ambitious form than the full-blown FX incarnation of Virtex-4. Second, they have done a considerable re-work of everything from their device- and process- verification procedures to their timing of market launches. As a result, we have this week’s announcement of Virtex-5 LXT, a 65nm high-density FPGA with SerDes transceivers capable of 3.2 Gbps operation at a stunningly-low 100mW power dissipation. These transceivers are functionally robust with both transmit pre-emphasis and receive equalization, but not overburdened with features as with some previous versions.
The new family is the second Virtex-5 line to be announced (more are expected to follow, including, if Virtex-4 is any guide, both an SX and an FX line. Xilinx says the new family is aimed at the “Triple-Play” challenge – voice, video, and data communications on a single network. By pruning down the SerDes to the most popular protocols and speeds and adding hardened support for the popular PCI Express and Gigabit Ethernet standards, Xilinx is helping to push high-speed serial design into the mainstream, while keeping device cost and manufacturability hazards to a minimum. By hardening the PCI Express block alone, Xilinx claims a savings of up to 10,000 LUTs and two watts of power, compared with soft-core implementations.
Based on the LX family, LXT will offer from approximately 30,000 to 330,000 logic cells (OK, they burned us on this one at first. This is actually 19,200 to 207,360 of the new, 6-input LUTs. Apparently Xilinx feels that each of the new cells is worth 1.6 of the old.) and from 360 to 960 standard user I/O pins (or up to half that many differential IO pairs). All members of the family come with one PCI Express endpoint block and four 10/100/1000 Ethernet MAC blocks. The series also has from 8 to 24 RocketIO transceivers. The family also includes block RAM, of course, ranging from about 1.3 to about 11.7 Mbits.
As we go to press, Synplicity is announcing synthesis support for the new family, so you can start synthesizing with Synplify Pro right off the bat. Synplicity and Xilinx are also collaborating on what they call the “Ultra High-Capacity Timing Closure Task Force” (UHCTCTF? Clearly the “pronounceable acronym police” were on holiday.) The purpose of this effort is to provide a smooth synthesis and place-and-route flow to handle the increasingly difficult timing-closure problems inherent in large designs at small geometries.
Xilinx says that software support for the new family is available this month, and engineering samples are now shipping to selected customers under the Xilinx Early Access Program in LX30T, LX50T and LX110T densities. LX85T and LX330T are expected to follow over the next six months. Pricing is typically cryptic with estimates of $109 for the LX30T in 1,000-unit volumes in 2008. With the same caveats, LX50T is estimated at $189, and LX110T is $529. Xilinx also says that it will be offering “ready-to-go” protocol solutions kits starting with the PCIe solutions kit in November 2006.
Clearly this is a more cautious and measured launch than we’ve seen from Xilinx in previous generations. It seems the company is maturing in its marketing and learning from past experiences as they face the challenges of launching ever more complex and diverse devices into an increasingly broad and uninformed market. In that environment, it takes far more than a few samples of silicon to get a new family off the ground and successfully satisfy new customers. Xilinx seems to have embraced that reality with its more conservative calendars and coordinated efforts in silicon, software, IP, development platforms, and methodologies.