Wind River Zooms In
This time, Wind River is touting a new release of their “Commercial Grade Linux” product line. WR’s Linux offering is always based on an unmodified version of Linux (in this case 2.6.14 replacing the company’s previously-supported 2.6.10). As such, each new Wind River release gains the benefits of the new Linux release in addition to the new features and patches that WR has included in its add-ons. According to the company’s announcement, 2.6.14 includes ” …hardware-specific drivers for additional processors and boards, updates to development tools, real-time performance and scheduling-related patches, high resolution timer patches, security, networking updates to … Read More → "Wind River Zooms In"
FPGAs at DAC
Despite some popular speculation, “DAC” does not stand for “Declining ASIC Commiseration.” The Design Automation Conference is a robust and lively gathering of companies, customers and comrades sharing a common interest in the progressive automation of the electronic design process. As we’ve discussed the past couple of weeks, however, the historical focus of DAC has been on the custom and semi-custom digital IC design process. Sure, there have always been other disciplines and interests represented, but the money, the momentum, and the fear have always been centered around the completion of complex IC designs and the … Read More → "FPGAs at DAC"
Electronic Elitism
The 43rd annual Design Automation Conference (DAC) got underway yesterday in San Francisco, California. The technical sessions have begun, the exhibits are open, and the parties, PowerPoints and pejoratives have now commenced. Last night, at a media, analyst, and customer briefing dinner at the San Francisco Museum of Modern Art, Walden Rhines, Chairman and CEO, hosted a customer presentation explaining how Mentor’s new Caliber nmDRC accelerates nanometer design rule checking by “hyperscaling” – a technique that takes efficient advantage of multiple processing elements to deliver many times the previous performance in giant DRC runs.
Electronic Elitism
Beyond promoting the polygon-pushing power of parallel processing, Mentor’s presentation also highlighted an interesting reality of today’s Electronic Design Automation (EDA) industry – nanometer class design tools are getting bigger, faster, more sophisticated, more expensive, and consequently, more exclusive. Among the customers heaping praises on Caliber nmDRC for its parallelizing prowess were AMD and Intel – hardly the novice class in semiconductor design.
It is no secret that the number of ASIC and COT (customer-owned tooling) design starts has declined steadily over the past several years and is forecast to continue declining for the foreseeable … Read More → "Electronic Elitism"
DAC Previsited
Exactly 299 days before “Cramming More Components onto Integrated Circuits” was published in Electronics Magazine, the first workshop of the SHARE Design Automation Project was held in Atlantic City, New Jersey. The SHARE workshop had papers with titles like “A method for the best geometric placement of units on a plane” and “Design automation effects on the organization.” The magazine article began with the statement “The future of integrated electronics is the future of electronics itself.”
With such generic paper titles and such an auspicious article intro, what has transpired since then that has inexorably linked those two … Read More → "DAC Previsited"
DAC Previsited
With such generic paper titles and such an auspicious article intro, what has transpired since then that has inexorably linked those two seemingly obscure technical publication events? Pretty much everything.
15,071 days later (this coming Monday, in fact,) the 43rd annual Design Automation Conference (DAC) will kick-off in San Francisco, California.
The SHARE design automation workshop, held in Atlantic City in June 1964, is now counted as DAC #1. The Electronics Magazine article, published less than a year after that seminal if inauspicious design automation event, contained a small section that threw down the gauntlet to the fledgling … Read More → "DAC Previsited"
System-Level Sideshow
He pauses for exactly the right amount of time, then whips into his delivery with energy and zeal – “Have youuuuu been struggling to meet ever-tightening design schedules with more complex designs and a smaller, leaner design team?” He picks up the pace, enunciating each word with perfect clarity. “Do youuuuu find that the RTL methodology is too cummmmmbersome for today’s more sophisticated FPGA designs?” He widens his eyes as he meets the gazes of each member of the audience, conveying an ominous fear. “Are youuuuuuu suffering the pain and ravages of MOORE’s LAW?!?”
Going for Speed
It may be surprising that such careful engineering attention is required to gain the desired performance from this lowest echelon of racing – cars powered only by gravity and driven by kids aged 9 to 16. It might also be counter-intuitive that some of the most careful engineering for processor performance comes in the very lowest echelon of computing systems – devices where many tiny processors may be put on a single chip in a system that might sell for single-digit dollars at the retail level. Both, however, are driven by the same constraints. When power, size, and cost are all at … Read More → "Going for Speed"
Tooling up for 65nm
Every time FPGAs hit a new process generation, there is a buzz. People want to hear about the underlying architecture, learn how fast the new devices will go, guess at how much logic they’ll hold, speculate on whether we’ll need a small nuclear power plant to operate them, and marvel at marketing’s ability to take something already quite impressive and exaggerate it to the point where we have no idea what it can actually do. We tingle with excitement. We wait a year until actual devices are available. Then, when the magic moment comes and we … Read More → "Tooling up for 65nm"
