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Managing the Middle Manager

Middle Manager makes his way through the maze of chest-high walls, passing members of his team as he plans his morning, pausing a couple of times – pretending to understand what he’s watching as he peers into cubes where startled engineers suddenly switch from doing real work to doing things they think will look more like real work. This daily double-ended dance of deception lasts only seconds. Middle Manager moves on down the corridor, hoping to hear a hint of the mood in executive staff as he passes the cracked conference room door.

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Reprogrammable Logic Drives Automotive Vision Systems Design

Automotive electronics system development teams increasingly grapplewith the challenges of new industry standards and product features. An automotive vision system is an example of a design that must deliver improved performance, system integration and security.  In turn, these requirements dictate the use of Field Programmable Gate Array (FPGA) devices in an automotive vision system.

Many of the automotive vision systems now being developed specify several cameras in the design for different views, such as reverse, side and forward (Figure 1).  Depending on the application, the system designer can choose from among several types of … Read More → "Reprogrammable Logic Drives Automotive Vision Systems Design"

Short Stack with Syrup

Non-volatile FPGA is one of today’s oddest market segments. Bound by the ill-defined characteristic of “non-volatility,” the field of available devices is diverse from the ground up, with strikingly different architectures, approaches, and benefits. Actel, long the leader in non-volatile FPGAs, began with antifuse technology (which is one-time programmable) and followed later with flash-based FPGAs. QuickLogic fielded an antifuse-type approach from the beginning, and Lattice Semiconductor joined the fray over a year ago with their LatticeXP hybrid devices, embedding a flash boot PROM on the FPGA for rapid, on-chip configuration.

In announcing their … Read More → "Short Stack with Syrup"

Is it February? Then it must be embedded world

When you come out of three days of hard-sell briefings from company spokespeople at an event like Nürnberg’s embedded world (lower case e and w – exciting in German), sometimes the trends in the industry are obvious: a couple of years ago everybody was briefing on their new ARM-based microcontrollers. This year there were far fewer certainties. The only immediately obvious threads were tabletop football (soccer) and robots. In the entrance area, Fujitsu had a huge set-up with space for what looked like a dozen players, and several stands had people twirling the rods on standard-sized … Read More → "Is it February? Then it must be embedded world"

Doin’ Hard Time

If the concepts of “Linux” and “Real Time” are stored in different sections of your brain, you are not alone.  Real-time Linux has always felt to me like a kind of operating system oxymoron – analogous to a hybrid SUV or a concrete canoe.  In my mind, Linux’s heritage was the land of virtuality, dynamic allocation, and squishy priorities – all catch-as-catch-can on processor strokes.  In such a place, the idea of soft real-time is palatable.  You can imagine Linux “trying real hard” to get to your process … Read More → "Doin’ Hard Time"

Un-structured ASIC

In the continuum of custom logic device technologies reaching from highly-custom Standard Cell ASIC at the high end to FPGA at the low end, we seldom hear from the node called “Embedded Arrays.”  The extremes get lots of publicity.  There is ample press and activity focused on both ASIC and FPGA, as these technologies are fairly easy to understand, and their benefits, problems, and trade-offs are quite familiar.  The middle is a little fuzzier and (usually unjustifiably) frightens away analysts, press, and even development teams. 

The “structured ASIC” flavor … Read More → "Un-structured ASIC"

Software Supervision

The latest version of your system is past primary development and ready for regression testing.  You’ve got just a few systems available, and they’re in a lab under the watchful eyes of the hardware development team.  Your software development and QA groups are ready with a bevy of regression tests, but access to the working prototype hardware in the lab is the tricky part.  Complicating the problem, your developers and QA engineers are scattered across three continents in six different time zones.  How do you coordinate use of the hardware for … Read More → "Software Supervision"

ISE Storm

For system designers, Moore’s Law is a gravy train.  Every couple of years, you get more gates, more speed, less power consumption, and lower cost.  For digital designers and tool developers, however, that gravy train is headed through the tunnel right at you.  Every couple of years, you have more gates to design in less time, more complexity to overcome, and tougher verification problems.  Your design tools are heavily impacted, too.  The old synthesis and place-and-route runs that took a few minutes on an old 200MHz Windows 98 laptop are now running for 24 … Read More → "ISE Storm"

Actel Activates Platforms

FPGA-based system-on-chip platforms are the etch-a-sketches of embedded design.  You can quickly sketch out your embedded computing system, use it, and easily erase and re-construct it in place as design changes are required.  Need a different peripheral?  No problem, just reprogram it.  Need to change a protocol – another simple hardware and software modification.  Want to use a different processor core – or an additional one?  Just drop it in and re-program the chip.  Your same board keeps right on working.

Actel is the alternative FPGA supplier.  On the … Read More → "Actel Activates Platforms"

Soft Processing and Customizable IP Enable Flexible, High Performance Embedded Design

Which would you prefer for your next embedded project: flexible system elements so that you can easily customize your specific design, or extra performance headroom in case you need more horsepower in the development cycle? Why should embedded engineers put themselves under undue development pressure and settle for one or the other? Soft processing and customizable IP offer the best of both worlds, integrating the concepts of custom design and co-processing performance acceleration into embedded design.

Embedded engineers often struggle with the challenges of improving performance or changing system characteristics after they have already completed the general … Read More → "Soft Processing and Customizable IP Enable Flexible, High Performance Embedded Design"

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