Logic Lockdown
Reverse engineering is not a back-alley, cloak and dagger, business-in-the-shadows affair – quite the contrary, in fact. Companies specializing in reverse engineering operate openly and have a long and public history, particularly in the semiconductor arena. In the United States, reverse engineering has the protection of law, with the Supreme Court ruling that “A trade secret law, however, does not offer protection against discovery by fair and honest means, such as by independent invention, accidental disclosure, or by so-called reverse engineering, that is by starting with the known product and working backward to divine the process which aided in … Read More → "Logic Lockdown"
Security Blanket
The year is 2010. Alone in the kitchen, 8 year-old Mikey pulls a cereal container down from the cupboard. He presses the “open” button. A tiny camera with a wide-angle lens grabs an image. Inside the lid, a low-cost embedded system with hardware video processing locates Mikey’s key facial features in the image and creates an identification map. It then downloads from the household wireless network a current database of the family members allowed access to that cereal at this time of day. Mikey is on the “disallowed” list. The lock holds fast. A text notification is already on its … Read More → "Security Blanket"
Security Blanket
Security is a growing concern in almost every type of system design today. Some applications have a more pressing need than others, of course. The consequences of Mikey subverting the automated cereal protection system and downing a few unauthorized grams of carbohydrates are far less severe than, say, a security failure in an airliner engine control system. Almost all systems these days have at least rudimentary security concerns. In a few cases, security is paramount.
A somewhat undesirable corollary to Moore’s Law might say that the more gates we have available, the more we’ll tend … Read More → "Security Blanket"
Complex ASIC Timing Verification Converges with FPGA-Based Designs
Over the past few years, as FPGA devices have increased in density, speed, and started embedding dedicated memory, multiplier blocks, high performance intellectual property (IP), PLLs, and high-speed SERDES, they have become a viable alternative to implement complex designs and applications that traditionally targeted ASIC or ASSP-based designs . This trend however is stressing the limits of traditional FPGA static timing analysis tools and designer productivity is affected.
To meet market requirements and achieve target performance, FPGA design engineers are adopting new design styles and complex clocking schemes (i.e. clock multiplexing in 10M, 100M, 1G … Read More → "Complex ASIC Timing Verification Converges with FPGA-Based Designs"
Catapult Levels Up
In my book, ESL is a serious contender for the title of “worst technical term of the decade.” As we’ve discussed before, the ESL label was possibly created by Dataquest in an attempt to create a category that could hold all of the EDA products that didn’t fit cleanly into any of the previously established tool categories. As such, ESL turned into more of a “bucket” than a “category” as it snowballed down the mountain of misfit design software, accumulating technologies such as transaction-level simulation tools, graphical block-based design environments, high level language modeling, behavioral … Read More → "Catapult Levels Up"
Catapult Levels Up
OK, maybe that last one wasn’t Dataquest’s fault.
Despite the shortcomings of the category, however, many of the products and technologies that have been labeled “ESL” are very promising in their own right. Mentor Graphics’s Catapult C is one such tool. We’ve discussed Catapult for a couple of years now, explaining its position as a power tool for the hardware designer – a product that takes a fully-behavioral ANSI C/C++ description of an untimed algorithm and explores the tradeoff space of hardware area/gate count, operating frequency, power, latency and throughput for single … Read More → "Catapult Levels Up"
Commercial Virtuality
Usually these companies developed their own “home grown” solutions – creating one-shot systems that simulated their particular hardware platforms, then deploying them to eager software development teams waiting to get started so they could avoid the long work nights and weekends associated with being the long pole in the project schedule tent. These simulators were generally thrown away as soon as they were used, making way for development of a new one for the next project.
SwitchCore, “Sweden’s Fastest Growing Company,” develops integrated switching chipsets for use in communications networks. SwitchCore’s devices are used in … Read More → "Commercial Virtuality"
Should You Reuse RTL?
Introduction
Ever since hardware description languages (HDLs) were first put into use to specify electronic designs, designers have recycled code. New insights into the use of these HDLs for design are gained by copying and modifying – with the requisite permissions of course – existing examples. By placing that code into the new designs, everybody saves time since designers do not needlessly re-invent an existing block of code. Someone spent significant time and energy to design that code block and other designers rightfully want to leverage that … Read More → "Should You Reuse RTL?"
Domesticating DSP
In the good old days, (those would be the EARLY 2000s) digital signal processing (DSP) was a well-behaved wild animal. It stayed outside in the pasture, grazed off the land, and never harmed the house pets. DSP didn’t disturb the neighbors and didn’t bite unless provoked. If we had a big, complex system, we often hired a specialist, a kind-of DSP whisperer, to handle the care and feeding of our little DSP. He knew all sorts of tricks and techniques for training and taming the little fellows. He spoke MATLAB. He was fluent in DSP … Read More → "Domesticating DSP"
