Articles – Page 549

June 17, 2008

In yet another installment of how life has gotten complicated in the design-for-manufacturing (or design-for-yield) world, we re-enter the world of the modern designer as contrasted from those of yore. Erstwhile designers followed rules, and, assuming the designs passed their tests on the way from design to manufacturing, the designer could give him- or herself a well-deserved pat on the back, release a satisfied sigh, and move on to the next project. What happened to the design at that point was not of concern to the design engineer because the design had escaped the realm of design. … Read More → "Faster Space Exploration"

A Passel of Processors

NVIDIA’s Tesla T10P Blurs Some Lines

by Kevin Morris

June 17, 2008

Picture this architecture – a high speed application processor doing control coupled to an accelerator comprised of a mass of processing elements ready to power-parallelize compute-intensive components of a complex problem. Sound familiar? Supercomputers have taken advantage of acceleration using schemes like this for a while. People using FPGAs for co-processors do it all the time.

Now, picture a new chip with 1.4 billion transistors, an array of 240 cores, and a processing throughput equivalent to about 1 TeraFLOPS. Many readers of this publication would probably guess a new FPGA, right?

A Passel of Processors

NVIDIA’s Tesla T10P Blurs Some Lines

by Bryon Moyer

June 17, 2008

Broken Design Flows and Point Tools

by Dick Selwood

June 10, 2008

Where do you go for help when your design flow is broken? Wally Rhines of Mentor Graphics wants it to be to him and his company. He feels that the EDA tool chain breaks every 2.5 process nodes (and has some convincing PowerPoint slides to back his case), and that 45 nanometre is the next inflexion point.

Stemming from this he argued, when giving a Globalpress Electronics Summit Keynote, it takes a broken tool chain to get engineers to adopt new tools. And who can blame them? Apart from the cost of purchase, it is hard work changing to … Read More → "Broken Design Flows and Point Tools"

Shortening the Rope

LDRA Checks Cert C and MISRA C++

by Bryon Moyer

June 10, 2008

Once upon a time, a man was given a rope and was told that it would be useful for many things. That most anything could be done with that rope. And the man tried it out, found some things easy to do – tying a bow, for example – and some things hard – intricate cat’s cradle, for example. He found that he could tie large crab traps together on such a rope and run them out to sea and retrieve them later. But he also learned that having his foot in a coil as … Read More → "Shortening the Rope"

Performance Improvements with New Secure IP and FAST Simulation Mode Models

by Bryon Moyer

June 10, 2008

Today’s high-capacity and high-performance FPGA designs are becoming more complex and require more third-party intellectual property (IP) cores. These hard IP blocks include pecialized high-speed multi-gigabit transceiver (MGT) I/O cores, PCI Express cores, clock management modules, FIFOs and complex processor cores, such as the PPC440 in the Virtex5 device. The DSP clock management cores (DCMs), BlockRAMs, and FIFO models are in a class of Hard IP cores provided in standard libraries because the simulation models do not require source code protection. However, the other class of Hard IP cores, which includes MGT I/O cores, PCI … Read More → "Performance Improvements with New Secure IP and FAST Simulation Mode Models"

Employing an I/O Interlocutor

FMCs Decouple FPGAs from Complex I/Os

by Bryon Moyer

June 10, 2008

It used to be so simple. PLDs provided a medium by which you could create and modify logic without having to make any board changes. All the variability was on the inside; the outside consisted of I/Os, and, back in the day, that meant one thing: TTL. Eventually, when CMOS became more prevalent, the less-often-used rail-to-rail CMOS interface was available, but those I/Os were on different devices that were dedicated to the CMOS low-power market.

Well, the first hints that the age of innocence was coming to an end appeared with … Read More → "Employing an I/O Interlocutor"

Shortening the Rope

LDRA Checks Cert C and MISRA C++

by Bryon Moyer

June 10, 2008

Sticking to Plan

Javelin and Magma Move Floorplanning Towards Production

by Bryon Moyer

June 3, 2008

Floorplanning has become an important step in SoC design because it lets designers and managers get an early sense of what can be accomplished on a given piece of silicon. This is, of course, critical during the never-ending negotiation between design and marketing as to who’s on drugs and who’s sandbagging. It’s more or less the equivalent of doing furniture planning, where you draw a picture of a room and cut out rough scale versions of the furniture and move them around to get a rough sense of what will fit. Not particularly … Read More → "Sticking to Plan"

New Toys

by Dick Selwood

June 3, 2008

When you are exposed to around 40 companies presenting their latest and greatest products or philosophy, it is sometimes a little difficult to keep the b……t filter in full-on mode. On your behalf, I tried to be as cynical as possible at the Globalpress World Summit in San Francisco, trying to see through each professional presentation and slick use of PowerPoint to establish whether there was a grain of truth in its heart. (Of course all of us at Techfocus are experts in finding that grain of truth – but normally we get more than a few … Read More → "New Toys"