Legacy of Languages
Using VHDL or Verilog to design FPGAs is just plain wrong.
Talk with any expert in languages, in logic synthesis, in hardware architecture. If you get past the “but that’s how we do it” layer of defenses, you’ll pretty quickly uncover a vast ocean of oddity that will make you wonder just why anyone ever considered the idea of doing FPGA design with HDLs, let alone how HDL-based design became the de-facto standard.
First, taking VHDL as an example: most of the things you can write in VHDL … Read More → "Legacy of Languages"