Hardware designers are a proud and detail-oriented group that takes great personal pride in the product of its efforts. Many engineers are drawn to hardware design—rather than, say, software work—to give their detail-oriented nature room to thrive. As early as their first freshman lab exercises, budding hardware designers learn that a software bug can easily be fixed by editing a text file and recompiling (though admittedly those who learned during the punch-card era may disagree with this attitude). But a hardware design error can be far more costly to one’s social schedule. A hardware design flaw might mean completely re-doing a wire wrap board instead of enjoying that Friday night trip to the pub. Suffice to say, lessons about the importance of up-front validation are strongly reinforced from the very beginning. Shared experiences like these have spawned a culture of thoroughness and pride in quality among hardware designers.
Hardware project managers, due to their role in the organization, are often required to be more practical and pragmatic. They serve as a bridge between the act of hardware design and that of running a business. These project managers work with Marketing to determine product requirements and to set a product release timeline with the intent of meeting an identified revenue or market share target. Hardware project managers also work with upper management or the Finance department to determine cost budgets that ensure overall profitability. In other words, hardware project managers serve to constrain the hardware design process and direct it toward the overall business goals of the organization.
But hardware project managers always need to exercise care, and think about how they affect the hardware design process. Their policy measures must meet practical business needs and still preserve the hardware designers’ intrinsic motivation to strive for high product quality. Increasingly, managers are looking for solutions to this conundrum. Design tools are an appropriate area of consideration, since they can improve overall productivity without necessarily imposing drastic changes on the way hardware designers work.
Slow Design Flow? Where to Look for the Culprit
When productivity problems afflict the design process, the culprit may well be found in the RTL synthesis steps. RTL synthesis is compute-intensive. In fact, it’s a likely candidate to be one of the top three time-sinks in the FPGA design flow, just below Place and Route. First, RTL synthesis runs syntax, semantic and electrical checks on the HDL source code. Next, RTL synthesis is used to generate a set of golden timing constraints and a netlist to kick off the back-end flow. Subsequently RTL synthesis re-enters the flow through an ECO or in some cases through timing closure efforts. With all these operations to perform, RTL synthesis is frequently guilty of using more than its fair share of the time budget. And examining tool usage can yield some “low hanging fruit” that is easy to pick yet effective in solving the productivity problem.
Hardware design schedules and costs can benefit from the early and consistent use of an incremental synthesis approach, which can significantly reduce runtime. Incremental synthesis recognizes specific areas of the design that have changed from the previous run. It spends its time re-synthesizing only the portions of the design that have changed, while unmodified portions are effectively reused. The ideal incremental synthesis approach recognizes design sameness despite changes made to commented text and does not sacrifice circuit quality or performance (that would defeat the purpose!). Moreover it does not require significant changes to existing design processes and it yields repeatable results. For maximum benefit, an ideal incremental synthesis flow will offer integration with back-end flows also.
The hardware design team that uses this sort of incremental synthesis approach throughout the design flow will see reduced tool runtime for many if not all RTL synthesis-related tasks. Moreover, these designers will see these improvements without significant disruption to their established design flow.
Two Ways to Boost Back-End Productivity
Where the opportunity exists, the incremental synthesis approach can be extended to improve runtime for Place and Route iterations also. There are two different ways to accomplish this today.
The first method is the simplest, requiring no up-front changes to the design flow. It attempts to leverage a prior placement, along with repeatable synthesis results, to guide the next placement. In addition to the runtime savings benefit, this flow also improves the ability of the Place and Route tool to provide more repeatable results, reducing the risk of introducing timing closure issues with a small change to the design. The Xilinx tools offer this in their “SmartGuide” flow; other back-end tools offer similar solutions.
The second approach involves a bit of up-front planning and requires splitting the design into smaller blocks. The RTL synthesis tool imposes hard boundaries around each of these blocks and treats it as a separate target both for synthesis and for the back-end. Ideally, the blocks should be split out such that timing paths from one block to the next have sufficient positive slack without requiring any cross-boundary optimizations. Once the blocks are drawn, not only is the RTL synthesis tool able to skip synthesizing unchanged blocks, but also the back-end tool is able to completely skip Place and Route on those blocks. Again, this approach offers significant runtime savings and also improves the ability of the Place and Route tool to provide repeatable results. The Altera tools offer this in their “Incremental Compilation” flow and other back-end tools provide a similar approach; the Xilinx “Partitions based” flow is an example.
Press “1” for Incremental Synthesis
Precision RTL Plus Synthesis from Mentor Graphics offers a push-button incremental synthesis flow, yielding 70% runtime savings1 when used together with the back-end flow. Furthermore, there is no additional learning curve required for a comfortable Precision RTL user to start benefiting from the push-button incremental synthesis flow in Precision RTL Plus.
The successful manager of a hardware design team is able to leverage the intrinsic strengths of team members, while addressing productivity culprits in a way that does not compromise product quality. Encouraging the early and consistent use of incremental synthesis can be an effective way to reduce project cost and schedule, without imposing significant restrictions on the hardware design team.
1. “Mentor Graphics Precision Synthesis Combined With Xilinx SmartGuide Technology Dramatically Reduces Design Time”, December 11, 2007, http://www.mentor.com/company/news/precisionsynthesisxilinxsmartguide
