In the past, physical synthesis tools for FPGA design were targeted to the advanced user and provided support for only a limited subset of devices. This has largely restricted the wide adoption of the technology. As a result, the Electronic Design Automation (EDA) tools have been inadequate in supporting the performance capabilities of the FPGA fabric. This article will examine the currently available FPGA physical synthesis tools and how a new generation of physical synthesis technology can help achieve timing closure faster, easier, and for a wider range of FPGA devices.

Why care about … Read More → "New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support"

Bonnnngggg…

Two thousand and seven creeps quietly toward a dignified death, trailing tales of victory and woe in the vast vortex of its widening wake.

Bonnnngggg…

Two thousand and eight eases expectantly into view, its perils and possibilities awaiting their unwitting victims and victors with equal voracity.

Bonnnngggg…

Mister Moore is a maddening mistress.

Naught seven was a year of hunker down and deliver.  In terms of new product announcements in the FPGA sphere, it was a year of bolster and boost, respond … Read More → "Auld Langxiety"

Using CPLDs to Replace or Augment Microcontrollers

With the advent of low-power CPLDs, electronic product designers now have new options for implementing many of the functions traditionally performed by microcontrollers. This article discusses several ways design scenarios that are advantageous to use a CPLD instead of a microcontroller, and when it makes sense to use a CPLD as a companion to a microcontroller.

Introduction

Tell a group of portable electronics designers that there is a low-power digital device that … Read More → "Using CPLDs to Replace or Augment Microcontrollers"

Pushing programmable logic into portables is a power play.  Portable devices put power consumption at a premium, and silicon vendors looking for a socket have to answer for each and every coulomb consumed by their chips.  Of course, they’re also interested in absolute minimal cost and board real estate, so getting a programmable device into your portable is unlikely at best.

Now, Altera’s somewhat uncategorizable Max II family is adding a super-stingy “zero power” (meaning “not very much power”) Max IIZ version to the lineup.  Altera … Read More → "Zeroing in on Power"

Using VHDL or Verilog to design FPGAs is just plain wrong.

Talk with any expert in languages, in logic synthesis, in hardware architecture.  If you get past the “but that’s how we do it” layer of defenses, you’ll pretty quickly uncover a vast ocean of oddity that will make you wonder just why anyone ever considered the idea of doing FPGA design with HDLs, let alone how HDL-based design became the de-facto standard.

First, taking VHDL as an example: most of the things you can write in VHDL … Read More → "Legacy of Languages"