feature article
Subscribe Now

Preaching to the Choir

Proselytizing Programmable Logic

The faithful are easy. An FPGA company rolls out a new line and the bragging begins: “More LUTs, increased Fmax, Shorter PnR runs, faster MGTs!” 

The faithful are impressed: “Yes! Tell us more! Have you increased the LUT width? Added more FF’s to your LEs? Diversified your mix of hardened IP blocks? Increased the BRAM ratio? ” 

(The Faithful talk like that most of the time – all acrimoniously acronymic, feasting in their insider insight, devouring the minutiae with reckless abandon, disdainfully dismissing the unwashed masses.)

The rest of the world, however, is less easily amused:  “FGP- what?  Can I make a digital camera out of one?  Or is this a new name for the LPGA?  What’s a LUT?”

If you’re trying to evangelize a technology – to spread it into new markets – you won’t get very far preaching to the faithful.  They’re already on your team.  You need to reach out to the broader audience.  The key is to go to where they are ideologically.  You need to understand the locals and learn their language.  Then you can bring them your message in a technology mission of sorts.

If you haven’t noticed, the past few years have seen FPGA companies launching missions in a number of villages around the land.  They wanted to win over DSP designers, so they started speaking primitive MATLAB and Simulink.  They learned to spell FFT.  Instead of talking about how many fewer timing violations you’d get with new synthesis options, they waxed on the benefits of parallelized multiplication.  It was a worthy first effort.  Better than marketing baby-back ribs to vegans, but still a bit lacking in results.  A few of the more adventurous signal processing folks swerved into the FPGA lane and started accelerating their designs to autobahn speeds.  Most of the market, however, continued with their DSP processors, unaware and unimpressed.

Next came the embedded systems market.  Attacking that group is a little like saying your target demographic is “people with hair.”  FPGA companies did a nice first effort here as well.  “Hey, we can put a 32-bit RISC machine on an FPGA…” 

Unwittingly, they had tapped into a DIFFERENT base’s “faithful.”  “Oh yeah?  Can I simultaneously boot Linux, Windows CE, and Nucleus with memory management on one and hard real-time constraints on another – all insulated through the security of an embedded hypervisor and debuggable with a remote-hosted, virtualized, Eclipse-based multi-core IDE while running an embedded relational database with cross-partition access for varying levels of security in qualified applications written in various dialects of C++, Ada, Java, and FORTH?”

“(Ulp!) We, uh, have on-chip block RAM.”

“Do you also have embedded flash (with load-leveling), DDR3 interfaces, multi-port RAM and predictive branch execution when running multiple soft-cores in an ASMP configuration?”

“Hey, can I offer you a souvenir USB memory stick?”

Over time, however, FPGA evangelism has gotten more sophisticated and more focused.  Happily.  One of the earliest examples was a result of Xilinx’s “vertical marketing” efforts way back around the turn of the millennium.  (Wow, that makes 9 years sound like a LONG time, doesn’t it?)  Xilinx had basically established a set of marketing groups, staffed primarily with highly experienced marketers from specific vertical areas… aerospace, automotive… (and those are just the “A’s”).  They acted like translators from FPGA-ese to the native language.  “We don’t talk to automotive designers about LUT counts – we talk about CAN bus.”  When applied to specific market opportunities for programmable logic infiltration, these groups were highly effective.  

More recently, and to a greater extreme, QuickLogic re-invented their entire company around the notion of hiding the FPGA-isms of their FPGAs.  Instead of slipping a vertical marketing group alongside their horizontal marketing groups, they went whole-hog into the ruse. (Sorry, vegans, that was two shots in one article, wasn’t it?)  QuickLogic had an advantage and a problem.  Their advantage was that their anti-fuse FPGA technology had excellent power efficiency, great stability, instant start-up, no configuration logic requirement, and comparatively high operating frequencies.  The problem was that they were also one-time programmable – which meant that FPGA designers (the Faithful) were put off by the lack of reprogrammability and the idea that they needed a Pez dispenser of FPGAs and a high-speed socket on their development board to do a project.  The solution?  Drop the “FPGA” label and invent a new term “CSSP” (Customer-Specific Standard Product).  Basically, they design some very cool applications using their (shhh, don’t tell – FPGAs) and you can call them up and order some – with customization options that make sense to you in your market for your application.  You don’t have to learn design tools, you don’t have to think about LUTs, synthesis pragmas, timing slack, or unroutes. You just pick the peripherals that you want with your core, and your chips arrive ready-to-run.  It’s kinda’ like ordering a sandwich.

Now, more companies are jumping on the “package for other markets” bandwagon in earnest.  Xilinx, in addition to their Virtex-6 launch, is highlighting a strategy that supplies “almost done” designs including purposeful development boards, a domain-specific range of IP, and reference designs that are just waiting for you to clip in that little “value added” part that distinguishes your product from the pack.  If you’re designing a triple-cantilevered franistan, and you see a development board with a double-cantilevered franistan all up and working out of the box, you can’t help but envision a way that this device could solve your problem. 

Actel too, is taking a shot at the lucrative uninitiated.  With their latest devices, they are beginning to offer not only reference designs, but a full-blown custom GUI that allows you to select the particular options you’d like to see in your finished chip – without ever pulling up an HDL editor.  They start with a traditional “reference design” style platform, but then they put on it a simple, domain-specific user interface that allows you to customize the implementation for your particular application.  In areas like power management or motor control, this may be just what the non-FPGA-o-philes are looking for.

As we move ahead, look for more companies offering FPGAs in sheep’s clothing.  The language they’ll speak will sound strangely familiar.  The problems they’re solving will be yours, and the FPGA-ese will be carefully muted in the background.  

Leave a Reply

featured blogs
Oct 26, 2020
Do you have a gadget or gizmo that uses sensors in an ingenious or frivolous way? If so, claim your 15 minutes of fame at the virtual Sensors Innovation Fall Week event....
Oct 26, 2020
Last week was the Linley Group's Fall Processor Conference. The conference opened, as usual, with Linley Gwenap's overview of the processor market (both silicon and IP). His opening keynote... [[ Click on the title to access the full blog on the Cadence Community s...
Oct 23, 2020
Processing a component onto a PCB used to be fairly straightforward. Through-hole products, or a single or double row surface mount with a larger centerline rarely offer unique challenges obtaining a proper solder joint. However, as electronics continue to get smaller and con...
Oct 23, 2020
[From the last episode: We noted that some inventions, like in-memory compute, aren'€™t intuitive, being driven instead by the math.] We have one more addition to add to our in-memory compute system. Remember that, when we use a regular memory, what goes in is an address '...

featured video

Better PPA with Innovus Mixed Placer Technology – Gigaplace XL

Sponsored by Cadence Design Systems

With the increase of on-chip storage elements, it has become extremely time consuming to come up with an optimized floorplan with manual methods. Innovus Implementation’s advanced multi-objective placement technology, GigaPlace XL, provides automation to optimize at scale, concurrent placement of macros, and standard cells for multiple objectives like timing, wirelength, congestion, and power. This technology provides an innovative way to address design productivity along with design quality improvements reducing weeks of manual floorplan time down to a few hours.

Click here for more information about Innovus Implementation System

featured paper

Fundamentals of Precision ADC Noise Analysis

Sponsored by Texas Instruments

Build your knowledge of noise performance with high-resolution delta-sigma ADCs. This e-book covers types of ADC noise, how other components contribute noise to the system, and how these noise sources interact with each other.

Click here to download the whitepaper

Featured Chalk Talk

uPOL Technology

Sponsored by Mouser Electronics and TDK

Power modules are a superior solution for many system designs. Their small form factor, high efficiency, ease of design-in, and solid reliability make them a great solution in a wide range of applications. In this episode of Chalk Talk, Amelia Dalton chats with Tony Ochoa of TDK about the new uPOL family of power modules and how they can deliver the power in your next design.

Click here for more information about TDK FS1406 µPOL™ DC-DC Power Modules