Library Science

ICs are made primarily with transistors, adorned here and there with the odd resistor or capacitor. The intentional ones, that is. Yes, the parasitics are everywhere. And we’re excepting DRAMs here. Their capacitors are odd, but in the bizarre sense, not in the rare sense.

And yet most IC designers never touch a transistor. Particularly digital designers. For them, transistors are buried deep below layers of abstraction, hidden safely inside the library, where all is dark and mysterious. Transistors can be summoned by describing behaviors in, say, C, from which they can be morphed into RTL, which then gets transmogrified into gates, which get munged into combinations of library cells, wherein lie transistors.

In order for most designers to be spared the indignity of managing individual transistors, someone has to do the work of making sure that the libraries are solid. And this is the under-appreciated task of the under-loved library team.

As described by Magma’s Steve King, the process goes something like this. A designer somewhere receives a high-level Verilog description of how a cell is supposed to behave. He or she creates, by hand, a transistor-level implementation of that functionality. We’re talking perhaps a few hundred transistors, although these folks are trying to get clever by adding differentiation, and that’s driving up the number of transistors. This is actually a problem – more on that in a moment.

Once created, this cell must be characterized, and that’s done by the library team. So the cell is handed to the team for them to mess with. Simple for the guy designing the cell. But picture yourself in the role of the library dude. You get handed a chunk of transistors, along with a non-synthesizable Verilog description if you want. It’s your job to simulate and characterize this block, and you have no more information to go on. Left on your own, you have to trace out the transistors to figure out how to stimulate and measure the cell.

This is where Magma’s SiliconSmart tool comes in – its role is to analyze the cell and provide a Boolean description of what’s inside, and then figure out all of the detectable transitions. This provides the library jockey something between transistors and behavioral Verilog to help guide the characterization.

The problem is that, as we noted before, these cells are getting more complicated. The number of transistors is climbing from a few hundred to as high as a couple thousand. Not only does this make the understanding of what’s in the cell more complicated, it also blows out the simulation times. A couple years ago, the simulation of an 800-transistor cell, including timing and noise analysis, would take 24 – 36 hours.

This is bad enough just from a productivity standpoint, but gets even worse when problems are found. These more complex cells have a lot of sequential content, and, without tricks to provide shortcuts, the sequential portions chew up 90% of the simulation time. And if a problem is found, it can take a long time to simulate from startup until the failure is reached for analysis.

Magma has come up with techniques for shortening this time, but they’ve also recently announced a significant new capability to speed up the understanding of the cell. It’s something they call functional recognition. They provide a series of rules and heuristics that allow SiliconSmart to traverse the cell and extract higher-level constructs.

In particular, the tool can recognize latches, flip-flops, asynchronous set and reset logic, combinatorial circuits, and pass-gate muxing structures. This is done using a combination of rule tables and pattern recognition.

Having a higher-level understanding of the circuit makes it easier to create “intelligent” test sequences. It can also provide insights on how long sequential trajectories might be shortened when it’s necessary to get to a particular state for diagnostic purposes.

Functional recognition helps the characterization engineer’s productivity more than the actual simulation speed, but it comes on the heels of a couple years of developing more clever simulation and more efficient characterization methodologies so that the 24-36-hour simulation of a couple of years ago can now be done in 5 hours using a farm of 20 CPUs. [confirming that the 20 CPUs applies to both before and after]

In addition to the base SiliconSmart tool, Magma has provided extensions in a couple different directions. The HP version uses FineSim SPICE to speed up the simulation time. Of course, fast SPICE simulators typically trade off some accuracy for simulation time, but this is the well-known cost of getting a result more quickly.

The DFM extensions allow for characterization with respect to systematic and random process variations. This adds a whole new set of things to think about as compared to the standard timing-and-power methodology. The simple recognition that process parameters can vary across the extent of a single chip changes the game dramatically; it’s no longer enough just to acknowledge that one chip will be different from another. Statistical methods must be extensively used to optimize yield curves, and by characterizing and optimizing library cells, the cells themselves can be made more robust, and the characterization information is made more useful to designers trying to manage the yield characteristics of their entire chip.

The SignOff extensions (which it appears can be applied to both the SiliconSmart and SiliconSmart HP versions) provide more detailed results: rather than just a single delay value, actual time-varying current or voltage waveform information is provided in standard CCS or ECSM formats (which we discussed in a bit more detail last year). You can also characterize power and signal glitch susceptibility to help designers of both cells and circuits ensure that their designs are rock-solid when all the bits and bobs on the chip start bobbing and weaving in concert, creating a veritable electronic cacophony.

Of course, all of this applies to digital circuits, not analog. As usual, the analog guys are on their own. For the time being, anyway. Magma is looking at providing such capabilities for analog; at present the focus is on the digital portions of such mixed cells as PLLs and SERDESes. The whole concept of a Boolean description or transition table for an analog circuit is suspect at best, so presumably such a tool would look and feel somewhat different as applied in the analog domain.

Given the predominance of digital cells, such tools can help assure the designer that by describing a concept way up at the RTL or C level, the transformations and transmutations and transliterations that will be applied before the design acquires actual transistors will yield a faithful, robust implementation of that concept.