Open-source operating systems (and specifically embedded Linux) have been making big gains in the device software space. Development teams are attracted by the lack of licensing fees and contracts, lower cost of ownership, perceived portability, and broad availability of the underlying software and source code. Unfortunately, some of the mechanisms that create these attractive benefits also carry hidden (and not-so-hidden) penalties. Finding the right release (distribution), finding or creating a test suite that matches that distribution, getting support (since software that comes from nowhere has nobody answering the phones), and tracking the current and appropriate versions for your application … Read More → "The People’s RTOS"
When FPGAs flirted with the million-ASIC-gate density for the first time, a bell went off in many designers’ heads. This was not the tinny tintinnabulation of a bouncy little bicycle bell telling them, “Be alert, cyclist coming through.” No, this was the foul, foreboding clang of calamity to come. This was the thousand-ton tanker train of timing-closure nightmares turning around to bear down on them again from a new direction, threatening to bring back that all-too recent memory of indeterminate iteration in their ASIC design process to cause chaos in their new, happy, FPGA lives.< … Read More → "Synplifying Physical Synthesis"
First, there are many “knowns” in the enterprise software space. Developers usually develop on the same hardware (host machine) and software platform (i.e. operating system) that their final product will run on. Usually, it is a well-tested and well- known development environment that hasn’t changed over the multiple products that the developer has contributed to. As a result, the software developer typically focuses on the application rather than the environment. Additionally, in the majority of enterprise applications, there is also no concept of real-time performance, determinism, or interrupts (outside of keyboard, mouse and network).</ … Read More → "The Challenges of an Embedded Software Engineer"
As system designers, we encounter the integration question at a much lower level. Processors, peripherals, memory, interconnect, and storage are all basic components of almost every modern electronic system design. A successful system designer has to balance the forces of form factor, power, price, performance, reliability, security, scalability, and product evolution in order to make the crucial decision of what and how to integrate, and what to leave discrete. While there are myriad options available, there is no reliable formula or roadmap to guide us through this complex engineering tradeoff.
As system designers, the first thing we … Read More → "Intelligent Integration"
Last year, with little fanfare, we presented our first annual FPGA Journal Reader’s choice awards. The response was fantastic, and everybody wanted to know how they could participate in this year’s awards process… It doesn’t work that way, of course. We use a super-secret balloting system and carefully guard the data to prevent any unscrupulous parties from tampering with the results.
This year, over 350 design teams answered our call to rate their experience with FPGA and EDA companies’ products and services. Each customer was required to answer based on … Read More → "Second Annual FPGA Journal Awards"
It’s time again to bring home that cake from the grocery store bakery, ditch the box, mess around with the frosting a bit so it looks more “homemade,” and tell the guests that you spent all afternoon baking it. FPGA Journal is turning 24 months old (that’s 11000 for those of you that absolutely can’t let go of binary math, even for a party). Since October 1, 2003, we’ve brought you hundreds of feature articles, thousands of press releases, a good number of controversies, and 104 weekly e-mail newsletters.
This week, in … Read More → "FPGA Journal Turns Two"
About twenty years ago, there were two well-known approaches to custom IC implementation. The first, which we called “Full Custom,” was the high-end methodology. Polygons were painstakingly pushed across Calma screens by determined designers working to eek out every ounce of performance from fiery five-micron silicon technology. Full Custom design was difficult and expensive – not for the faint of heart or the financially challenged.
The second option at that time was Gate Array. Gate Array was for product teams with deadlines to meet and more important things to do than fighting with design rule … Read More → "Rationalizing Reconfigurability"
Allan Cantle knows what it takes to design high-performance digital systems. He’s been proving it since his early days at BAE Systems, where he was creating real-time simulations of evasive enemy targets to be used with real-world missiles in targeting practice. Allan has always had a knack for decomposing a complex problem into manageable-sized chunks, then mapping those chunks onto the appropriate architectures with the right interconnect to hit aggressive performance goals in the most economical way. Allan has a passion for working on complicated computing problems and isn’t afraid of trying varied technologies to … Read More → "Allan Cantle"