Articles – Page 499

September 8, 2009

It is well known that formal verification offers exhaustive proofs of correctness and can help find deep corner case bugs. Verification engineers have typically relegated its use to block-level designs, preferring to use simulation, the tried and tested workhorse, for chip-level and full-chip verification. The very strength of formal verification, namely its exhaustiveness, is also its Achilles heel in that with design size growth, formal engines run out of steam due to state space explosion. Simulation, on the other hand, scales well with design size and doesn’t suffer the same fate as formal verification.

Linux or Commercial OS?

by Dick Selwood

September 8, 2009

Watching the season premiere of “Mad Men” last week got me thinking about hair styles and those skinny neckties of the early ’60s. Exactly what is fashionable? Ask that question today among embedded software developers, and you’re bound to get a simple, straightforward answer: Android. And while Android rightly deserves much of the attention, it’s not the “be-all, end-all” of operating systems in use today.

No doubt there’s been a lot of noise and enthusiasm for Linux and Android. In fact, many developers viewed the rise … Read More → "Linux or Commercial OS?"

Seven Steps to an Accurate Worst-Case Power Analysis Using Xilinx Power Estimator (XPE)

by Jim Turley

September 2, 2009

Seven Steps to an Accurate Power Estimation

As a necessary step in any FPGA design, power and cooling specifications need to be properly set in order to create a functioning and reliable system. In most cases, these thermal and power specifications need to be set prior to PCB design and, due to the flexibility of FPGAs, often the FPGA design is not completed or sometimes even started prior … Read More → "Seven Steps to an Accurate Worst-Case Power Analysis Using Xilinx Power Estimator (XPE)"

AES and Antifuses

FPGA Security

by Dick Selwood

September 1, 2009

You bring a new product to market, and, within weeks, a rival appears, one that is clearly a rip-off of your design: not just looking like yours or performing much the same functions, but actually a clone of your design. There are shed-loads of statistics that show that the problem is increasing within the electronics industry and a mass of anecdotal evidence that indicates that designs using FPGAs are being increasingly targeted.

As FPGAs have moved from simply mopping up glue-logic to becoming full-blown Systems on Chip (SoCs), so they now embody the key Intellectual Property (IP) … Read More → "AES and Antifuses"

Dante Enters a New Field

Or, is this Heaven or Hell?

by Bryon Moyer

September 1, 2009

Dante would feel right at home surveying the math required to create useful circuits. He might meet some argument as to whether he was observing hell or heaven, but there would be no disagreement on the levels one would encounter as one approached the deepest depths or highest heights.

At the first level, one finds the easy world of ones and zeros. George Boole governs this domain, and he holds dominion over a disproportionate swath of the landscape. Moving in a level brings us to the simple world of conservative law passive circuits. Voltage and current sources, … Read More → "Dante Enters a New Field"

Courage Under Fire Drill

Surviving Interruptions

by Bryon Moyer

September 1, 2009

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Power Consumption at 40 and 45nm

by Kevin Morris

August 31, 2009

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. This white paper details how Xilinx designed for this new reality in its recently introduced Spartan®-6 (45 nm) … Read More → "Power Consumption at 40 and 45nm"

I/O Design Flexibility with the FPGA Mezzanine Card (FMC)

by Kevin Morris

August 31, 2009

The FPGA’s inherent flexibility has proven indispensable for the creation of external I/O interfaces. However, unless I/O is implemented on a daughter card (mezzanine module), replacing the physical I/O components and connectors requires … Read More → "I/O Design Flexibility with the FPGA Mezzanine Card (FMC)"

Taking Advantage of Advances in FPGA Floating-Point IP

by Jim Turley

August 31, 2009

Recently available FPGA design tools and IP provide a substantial reduction in computational resources, as well as greatly easing the implementation effort in a floating-point datapath. Moreover, unlike digital signal processors, an FPGA can support a DSP datapath with mixed floating- and fixed-point operations, and achieve performance in excess of 100 GFLOPS. This is an important advantage, for many high-performance DSP applications only require the dynamic-range floating-point arithmetic in a subset of the total signal processing.

… Read More →

Catching Mr. X: Diagnosing CDC Errors in FPGAs

by Kevin Morris

August 25, 2009

One of the more popular board games of the 1980’s was Scotland Yard, a game of co-operation in which each player is a detective… except for the shady “Mr. X,” the villain. Over the course of the game, the team of detectives collaboratively chases Mr. X across the city of London. At various points in the game Mr. X appears to the detectives but then just as quickly disappears again. If the “good guys” are able to work together to execute a containment plan, they can catch Mr. X. If not, Mr. X … Read More → "Catching Mr. X: Diagnosing CDC Errors in FPGAs"