EEJournal

feature article archive
Subscribe Now

MachXO2 Overview

by Kevin Morris
November 17, 2009

The MachXO2 family offers designers of low density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Compared to its popular predecessor, the MachXO family, the MachXO2 family delivers a 3X increase in logic density, 10X increase in memory, over 100X reduction in static power, and up to 30% lower cost. In addition, the MachXO2 devices include hardened implementations of some of the most popular functions such as User Flash Memory (UFM), I2C, SPI and timer/counter, providing designers a “ … Read More → "MachXO2 Overview"

Accelerate Your System and Consumer Designs With MachXO2 PLDs

by Kevin Morris
November 17, 2009

The MachXO2 family offers designers of low-density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Built on a low power 65-nm process featuring embedded Flash technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power and up to 30% lower cost compared to the prior generation MachXO family.  In addition, several popular functions used in low-density PLD  applications, such as user Flash memory ( … Read More → "Accelerate Your System and Consumer Designs With MachXO2 PLDs"

Platform Manager Overview

by Kevin Morris
November 17, 2009

Platform Manager simplifies board management design significantly by integrating programmable analog and logic to support many common functions, such as power management, digital housekeeping and glue logic. By integrating these support functions, Platform Manager devices not only reduce the cost of these functions compared to traditional approaches, but also improve system reliability and provide a high degree of design flexibility that minimizes the risk of circuit board re-spins.

Watch this 5-minute video to:

< … Read More → "Platform Manager Overview"

FPGA Power Management and Modeling Techniques

by Bryon Moyer
November 17, 2009

This white paper discusses the major challenges associated with accurately predicting power consumption in FPGAs, namely, obtaining accurate signal activities, static power modeling, and dynamic power modeling, as well as how Altera addresses these challenges through the PowerPlay early power estimator and the Quartus® II PowerPlay power analyzer. This paper also presents the accuracy of the model by comparing predicted power consumption with actual silicon measurements using an extensive suite of real-world customer designs. Using these best-in-class power analysis tools, a designer can … Read More → "FPGA Power Management and Modeling Techniques"

FPGA Design Methods for Fast Turnaround (REVISED)

by Bryon Moyer
November 17, 2009

This paper takes an in depth look at a variety of techniques to help you speed up your synthesis iterations. Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.

… Read More → "FPGA Design Methods for Fast Turnaround (REVISED)"

Applying the Benefits of Network on a Chip Architecture to FPGA System Design

by Amelia Dalton
November 17, 2009

NoC interconnect architectures provide a number of significant advantages over traditional, non-NoC interconnects, such as allowing independent layer design and optimization. Altera’s Qsys system integration tool, included with the Quartus® II software, generates a flexible FPGA-optimized NoC implementation automatically, based on the requirements of the application. 

Author:  Kent Orthner, Sr. Manager, Software & IP, Altera Corporation

… Read More → "Applying the Benefits of Network on a Chip Architecture to FPGA System Design"
featured blogs
Human Artifacts Discovered on Mars!
Apr 24, 2026
A thought experiment in curiosity, confusion, and cosmic consequences....
More from Max's Cool Beans...