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Fill Solutions Are Getting Smarter

As the industry begins production at 45-nm geometries, one of the issues that needs to be resolved is that of planarity—the flatness of the IC after chemical-mechanical planarization. At 45nm and below, fill solutions become much more challenging, because manufacturing processes and physical interactions become more sensitive to small metal density variations.

A big part of the problem is that the allowable thickness variation has remained constant at +/-15%, even while the total thickness of wires has decreased. This dichotomy means that the percentage of total … Read More → "Fill Solutions Are Getting Smarter"

Decisions, Decisions, and Threads

The whole way through creating your SoC you are faced with decisions. Some of the hardest decisions, since they are the most difficult to change if they are later seen as sub-optimal, are those made at the architectural level. How do you assign the tasks that you need in order to produce the performance you want, at a reasonable cost in IP licences, silicon real estate, power consumption, and end product performance? For this part of the application, we really require the number crunching of a DSP, while over here we want the flexibility of running an OS, say … Read More → "Decisions, Decisions, and Threads"

Unpicking the Codes

We did think of “ARM for Dummies” as the title of this guide to the arcane, but ultimately logical, world of ARM architectures and processors, but since none of you are dummies and we were uncertain about the copyright position of “… for Dummies,” we decided not to. Instead here is a simplified map through architectures, implementations, and jargon.

ARM-based chips ship in the millions each week: the ARM website claims that 90 ARM processors are shipped every second! Over 200 semiconductor companies are shipping products with ARM processors in them. (Makes Intel Inside seem … Read More → "Unpicking the Codes"

Beyond the Usual Suspects

We often discuss the proliferation of programmable logic into a plethora of new projects.  We’ve chronicled the capacity of FPGAs to carry us outside the domain of tried and true wired and wireless data communications into a world of other markets like consumer, automotive, avionics, virtual ASSP, and more.  The thing is, while the chips may work spectacularly well in many of these application areas, the design methodology often doesn’t.  Sure, all of us old-timers have been fluent in LUT-ese for years, and we live and breathe utilization reports, PnR optimization tuning, and bitmap … Read More → "Beyond the Usual Suspects"

Not For Software Engineers

Wolfgang froze when he saw it. He had heard rumors that such things might be possible, that his job could one day be at risk, but he had more or less blown it off. Too many other things to worry about. And then… there it was. An automatic translation facility on the web.

He made his living painstakingly translating documents to and from German. He had always been convinced that computers could never do what humans did. But now he wasn’t so sure. Computers had completely trashed other careers that used … Read More → "Not For Software Engineers"

Big Software and Little Chips

Did you hear the one about Microsoft and the patent lawyers? They have to stop selling Microsoft Word!

No, seriously. Last week a judge found Microsoft guilty of patent infringement and ordered the company to stop selling Microsoft Word. Can we even imagine a world without Word anymore?

I think this case presents something of a Rorschach test for nerds. (Rorschach tests are those ink blots you’re supposed to describe to the psychologist. Everyone sees something different.) Some people jump up and down and clap their hands on hearing the news, shouting & … Read More → "Big Software and Little Chips"

Samplify Supercharges ADC

FPGAs end up in the thick of the datapath in most applications today.  Whether the device is bridging between incompatible protocols, blasting bits over a backplane, or performing massively parallel signal processing — in each of these cases, a massive data stream comes into our FPGA, gets munged around by all our wonderful FPGA fabric and internal blocks, and then the result is streamed out of our FPGA on its way to some final destination.  While much of our design focus is what goes on “between the I/Os,” the limiting factor is often the bandwidth of … Read More → "Samplify Supercharges ADC"

IP Interface Standards

Standards are a tricky business. They require cooperation between competitors to be successful. They require companies with well-entrenched proprietary positions at the feeding trough to yield some of that advantage so that others may feed alongside them. There has to be an overarching good that can be achieved – especially for the companies having to cede pole position. “Kum-bah-yah” and “this is good for the universe and your karma” won’t get very far. Even if there’s a really really good reason, PEGS LAW* will conspire to upset the best standardization effort. … Read More → "IP Interface Standards"

Dueling DACs

1888.  One thousand eight hundred eighty eight.  That’s the number of conference attendees reported in the “Preliminary Attendance Figures” for the 46th Design Automation Conference (DAC) held last week in San Francisco.  The press release proclaims attendance was up “more than 12% over last year.”  

Four years ago, in 2005, in an article titled “Ditchin’ DAC” I gave a brief history of the Design Automation Conference and wove a controversial tiny-tome telling why I thought the conference and the industry it represents were walking … Read More → "Dueling DACs"

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