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CEVA’s New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs

by Bryon Moyer
September 7, 2010

MOUNTAIN VIEW, Calif. – September 07, 2010 – CEVA, Inc. [(NASDAQ: CEVA); (LSE: CVA)], the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today introduced the CEVA-X1643™, a  highly-energy efficient,1 GHz DSP core designed to boost overall chip performance for a broad range of applications including wireline and wireless communications, surveillance, portable multimedia and more. The CEVA-X1643 is the latest family member of the widely used CEVA-X DSP architecture, which has been licensed by more than 25 customers and shipped in over 100 million devices to … Read More → "CEVA’s New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs"

Adeneo Embedded provides Windows Embedded CE 6.0 drivers for TI’s WiLink™ 6.0 connectivity solution

by Bryon Moyer
September 7, 2010

Bellevue, WA, USA, and Ecully, France, September 7th, 2010: Adeneo Embedded, a Microsoft® Windows® Embedded Gold Partner with facilities in Europe and in the USA, today announced availability of its Wi-Fi® and Bluetooth® technology drivers for the WiLink™ 6.0 single-chip solution (WL1271) from Texas Instruments Incorporated (TI) which support Windows Embedded CE 6.0 R3. The customizable, combined solution makes the design … Read More → "Adeneo Embedded provides Windows Embedded CE 6.0 drivers for TI’s WiLink™ 6.0 connectivity solution"

Non-Standard

Or, Will The Real Standards Effort Please Stand Up
by Bryon Moyer
September 7, 2010

It seemed pretty straightforward based on the press release headline: “Synopsys and IEEE-ISTO launch industry body to evolve Interconnect Modeling Standard.”

Always interested in filling yet another in my seemingly endless supply of pockets of ignorance, I made a couple phone calls to understand a bit more about what was being standardized.

And in so doing, I waded into something of a minor hornet’s nest. Actually, that’s a bad metaphor, because, had I done that, I would have been badly stung. As it is, I … Read More → "Non-Standard"

Psych!

FPGA History makes Tough Road for Ecosystem
by Kevin Morris
September 7, 2010

The “Peanuts” comic strip made the situation iconic.  Lucy would place the tip of the football on the ground, holding it upright with one finger (American-style football in this case – sorry international audience – bear with us, this is how one player holds the ball while another does a stationary-type of kick.) Charlie Brown is skeptical.  Lucy has tricked him with this before, waiting until the last instant, then yanking the ball away, causing him to fall head over heels in a nasty tumble.  She … Read More → "Psych!"

Next Generation Direct RF EdgeQAM Design

by Kevin Morris
September 7, 2010

Abstract

Quadrature Amplitude Modulation (QAM) serves as the gateway to deliver video content to the consumers by radio frequencies (RF) over coax cable. Universal Edge QAM or uEQAM residing in a transmission headend system takes a video transport stream in over Ethernet or fiber ports and modulates the video data over multiple RF frequencies. The traditional EQAM system uses low intermediate frequency (IF) interfaces and analog mixers to upconvert into … Read More → "Next Generation Direct RF EdgeQAM Design"

Implementing High-Performance FIR Filters and FFTs in 28nm FPGAs

by Kevin Morris
September 6, 2010

Finite impulse response (FIR) and fast Fourier transforms (FFTs) are two of the most common digital signal processing (DSP) functions implemented in FPGAs. In this webcast, you’ll learn how the FPGA industry’s first variable-precision DSP architecture, available in 28nm Altera® FPGAs, is optimized for FIR and FFT implementation.</ … Read More → "Implementing High-Performance FIR Filters and FFTs in 28nm FPGAs"

Lowering System Costs with Highly Integrated FPGAs & Power Solutions

by Jim Turley
September 6, 2010

Changing the architecture of electronic systems from parallel I/O to high-speed serial can be challenging. It involves learning a new I/O standard, designing PCBs for gigabit per second differential signals, and applying new debug and verification techniques, to name a few. One way today’s low-cost, low-power FPGAs can help ease these challenges is IP blocks implementing multi-gigabit per second transceiver I/Os (analog and digital circuits) and supporting many popular serial protocols (e.g. PCI Express).  In some FPGAs, such … Read More → "Lowering System Costs with Highly Integrated FPGAs & Power Solutions"

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