Abstract

Quadrature Amplitude Modulation (QAM) serves as the gateway to deliver video content to the consumers by radio frequencies (RF) over coax cable. Universal Edge QAM or uEQAM residing in a transmission headend system takes a video transport stream in over Ethernet or fiber ports and modulates the video data over multiple RF frequencies. The traditional EQAM system uses low intermediate frequency (IF) interfaces and analog mixers to upconvert into RF channels. This article discusses the design and implementation of an all digital EQAM modulator using an FPGA for the direct RF DAC interface without requiring expensive and bulky analog components.

Background

uEQAMs have taken off in earnest starting in 2009 and will likely continue to yield strong growth over the next four years due to demand for HD video contents. uEQAMs reside at the edge of a fiber network; turning the outgoing digital information carried by the network into RF signals for distribution to individual households.

The first wave of QAM deployment is likely to occur in markets where competition from IPTV is particularly strong, countries such as South Korea, Japan, and France. China may take a strong lead with their Next Generation Broadcast (NGB) infrastructure that will be deploying digital video over the next decade. Data Over Cable Service Interface Specifications (DOCSIS) are the standards used in EQAM. Up to 40Mbps can be achieved with DOCSIS 1.0, 1.1, and 2.0. The latest DOCSIS 3.0 can deliver up to 160Mbps for high definition (HD) video content.

The number of QAM channels per RF port has been doubling about every three years due to the increase of available silicon integration, yet power is still the largest issue facing the increase of QAM channels.

EQAM is primarily the RF modulation and transmission module extracted from a consolidated Cable Modem Termination System (CMTS). Because the CMTS has been divided into constituent parts in the modules, the EQAM needs a new interface to the Modular-CMTS (M-CMTS) MAC module. That new interface is an Ethernet interface, as specified in the Downstream External Physical Interface [DEPI], needed to communicate with the now remote EQAM.

EQAMs may also interface to video servers via an Ethernet interface and provide a downstream RF transmission to deliver digital video services.

With the advancement of digital entertainment and broadband technology, there are various ways to send digital information to end users such as cable and satellite subscribers. The current digital cable systems deployed around the world use the QAM standard that defines the input data framing structure, channel forward error encoding, filtering, and QAM mapping. In digital TV, the typical downstream signal uses either a 64- or 256-QAM scheme. The data source is typically MPEG2 or later H.264 transport packets (see Figure 1).

Figure 1. A Typical Block Diagram of a QAM Modulator

QAM is a form of modulation that is widely used for modulating digitized video, voice or data signals onto an RF carrier that can offer numerous advantages over other forms of data modulation such as Phase Shift Keying (PSK). QAM is a signal with two baseband carriers shifting in phase by 90 degrees and then modulated, resulting in an output that consists of both amplitude and phase variations. In view of the fact that both amplitude and phase variations are present it may also be considered as a mixture of amplitude and phase modulation. The amplitude and phase carry the digital contents.

The International Telecommunication Union (ITU) defines the J.83 transmission specification with Annex A, B, and C versions that describe the framing structure, channel coding, and channel modulation for digital multi-service television distribution systems.

The baseband modulator of the 8 channels QAM reference design includes the following feature requirements:

Support for QAM mapping and channel filtering of Annex A – 64, 32, 16, Annex B – 256, 64, and Annex C – 64 point constellations.
Support for simultaneous multiple annexes rates and QAMs. Different channels can have different rates and QAM at the same time.
The filter output is up converted from baseband to digital RF.

For simplicity, the forward error correction (FEC) blocks are not discussed since they are basically the same architecture for any QAM modulator.

Functional Descriptions

The J83 modulator fits between channel coding module (FEC, interleaver, scrambling, Trellis-coded modulation) and the Digital Upconverter (DUC). The DUC is designed with Altera’s DSP Builder Advanced Blockset (as shown in Figure 2).

Figure 2. Block Diagram of J83 Modulator

A null packet generator, which is used as an internal generated signal source, is attached to the TS input at a rate given by TS_data_refclk. The PCR enabled TS interface is used.

The traffic of the FEC Encoder is passed to the J83 modulator via an aggregation circuitry. The aggregator multiplexes/aggregates 8/16 streams of symbol data at 64Mhz into one Avalon stream at 256Mhz. The modulator first sends the corresponding symbol rate strobe to the FEC encoder (based on the Annex/rate configuration). The FEC Encoder returns the symbol data together with a valid signal. Data of all four channels within a block may be valid at the same cycle. The FEC output can be 4 to 8 bits depending on the constellation.

The input to the aggregator is 2/4 blocks of four channels while the output is 8/16 independent channelized TDM bus.

To simplify timing, the clocks of the FEC Encoder and aggregator logic are all provided by one PLL. The Quartus TimeQuest Analyzer will consider cross clock domain transfer as synchronous as all clocks are aligned at the rising edges. The aggregated FEC input is transferred to the modulator running at the same clock frequency but at a different phase. See the clock structure section for more information.

The QAM mapping/encoding function of the modulator takes the symbol data, maps it to the constellation assignment and generates both the I and Q symbols. Although I/Q symbols only have 16, 8, 6, or 4 levels (for QAM 256, 64, 32, and 16), 5 bits are used to represent the I/Q values. Now the TDM bus is fully utilized – 32 channels of a maximum of 8 MHz equals to 256 MHz.

The RRC channel filter takes the I/Q symbols and pulse shapes them according to the roll-off specifications. The output rate of the RRC filter is twice the symbol rate; therefore, two paths (Avalon buses) are needed. From this point on, there are two parallel processing paths. After the RRC, a gain section is added to return the signal to full scale at the worse case.

The SRC has to take data precisely as part of the sample rate conversion algorithm, therefore, a compensation FIFO is needed between the RRC and SRC. Write and Read status of the FIFO is available for debugging. Any overrun or under-run if it happens will show up here.

The SRC uses the same filter for all of the data rates, but different timing coefficients – input_sample_period and output_sample_period. By setting to different timing coefficients, SRC can convert the input to rates other than 16Msps (based on 4096 MHz DAC). For example, when a DAC of 4.608GHz is used, the same design can be reused by running it faster and set the resampled rate to 18Msps.

After SRC, there is a gain/attenuation section allowing 1dB increment/decrement from +6dB to -8dB. The SRC output maintains full scale for the worst case therefore; even one dB increment may cause saturation.

Saturation check is performed at all subsection outputs and overflow status is available, even though some sections are guaranteed not to overflow by design (these analyses are shown in Figures 3 and 4).

Figure 3. Frequency Responses of RRC Filters

Figure 4. Frequency Responses for combined RRC/SRC Filter

A digital upconverter (DUC) is a key component for all digital modulation transmission such as wireless or cable systems. The built-in hard multipliers and memories are the building blocks to design a digital converter. The primary role of the DUC is to filter, upsample, and modulate the baseband digital signal to either and IF or RF signal before converting to an analog carrier for transmission. The interpolation FIR filter is used for upsampling the baseband signal to some higher sampling frequency. Several interpolating filters can be cascaded to increase the output frequency. The FIR Interpolation block resamples the discrete-time input at a rate I times faster than the input sample rate, where the integer I is specified by the Interpolation factor parameter. This process consists of two steps. The first step is to upsample the input to a higher rate by inserting I-1 zeros between samples and the second step is to filter the upsampled data with a direct-form of FIR filter. The FIR Interpolation block implements the above upsampling and FIR filtering steps together using a polyphase filter structure, which is more efficient than straightforward upsample-then-filter algorithms.

An 8-QAM channel digital RF upconverter reference design includes the J.83B baseband modulator 5, the digital up-conversion (channel merger + up-sampling + carrier modulation), and LVDS interface (see Figure 5).

Figure 5. System Block Diagram

DSP Builder Advanced Blockset, which is a specification-driven blockset. The advanced DSP Builder is based on a synthesis technology that optimizes the high level, untimed netlist into low level, pipelined hardware targeted to the chosen FPGA and chosen clock rate. The advanced blockset provides constraint-driven design methodology through system level parameters. The desired fmax is specified, where the tool would insert the right amount of pipeline and maintain the data path algorithm accuracy.

The input to the DUC is provided by a pre-modulator. The pre-modulator performs the following operations:

Provides QAM channel input stream with 6MHz BW at Intermediate Frequency (IF) sampling rate
256 QAM mapping
Channel filtering using a root raised cosine FIR filter with roll-off factor of 0.12
Separate I,Q components

The DUC performs the following operations:

Up-sample to a digital RF rate
Frequency translation of all 6 MHz channels
Up-convert to RF carrier frequency between 55Mhz and 880MHz

Figure 6 shows the overall block diagram of the DUC with its different stages of up sampling

Figure 6. A Functional Block Diagram of a DUC

In this example, the 8 channel signals are up-sampled 16 times to 256 Msps using a series of interpolating filters. Then the up-sampled 8 channel signals are frequency translated to assigned center frequency at -21, -15, -9, -3, 3, 9, 15, 21 MHz by multiplying the I and Q components by cos(x) and sin(x) and add the results together. The summation of the eight channels with 6MHz spacing is a band of 48 MHz signal.

The 48 MHz band is further up-sampled 16 times to 4096 Msps using another series of interpolating filters. Then the signal is up-converted to RF carrier frequency of 860 MHz by multiplying the I and Q components by cos(x) and sin(x) and add the results together. Due to the fmax limitation of FPGA, the interpolating filters and RF carrier modulation must be implemented using M-parallel branches (see Figure 7)

Figure 7. The DSPBA Implementation of DUC Design

1st Interpolating by 16 Filters (before 256 MHz)

The interpolating filters perform a 256 MHz/16 MHz = 16x up-sample and low pass filtering to preserve the input bandwidth while preventing aliasing due to the up-sampling process.

The 16x up-sampling is broken down to 4 stages of half-band filters to use fewer multipliers. The half-band filter has the property that except for the center coefficient, all the even index coefficients are zero. Each half-band filter increases the output sample rate by 2 (as shown in Figure 8)

Figure 8. Spectrum Mask of Half-Band Filter

Second Interpolating by 16 Filters (after 256 MHz)

The interpolating filters perform a 4096 MHz/256 MHz = 16x up-sample and low pass filtering to preserve the input bandwidth while preventing aliasing due to the up-sampling process.

Polyphase NCO

Direct RF uses a numerically controlled oscillator (NCO) to generate digital RF carriers. As a result, the carrier frequency is limited by the Nyquist theorem to half the sampling rate of the NCO. The sampling rate of the NCO is the design is 256 MHz. For DAC with GHz sampling frequencies, a polyphase modulation scheme was proposed that utilizes the high-speed, low-voltage differential serializer (LVDS) embedded in the FPGA to achieve higher-than-Nyquist frequency RF carriers.

To synthesize RF carrier at 4.096 GHz RF sampling frequency, we need 16 NCOs to carry 16 phases of the 860 MHz sinusoid.

Summary

There are two important parameters often used to characterize digitally modulated signals; bit error ratio (BER) and modulation error ratio (MER). BER is one of several performance metrics used in digital data transmission. For instance, if a 1 is transmitted and it’s subsequently received as a 0, the result is a bit error. BER is measured or estimated by transmitting some number of bits, and comparing the number of incorrect or errored bits received at the other end to the total number of bits received. In general, BER is the ratio of errored bits to the total number of bits transmitted, received, or processed over a defined amount of time. Mathematically, two formulas are often used to describe BER:

BER = (number of errored bits)/(total number of bits)

BER = (error count in measurement period)/(bit rate x measurement period)

MER is more dependent in the QAM constellation type. MER is defined as the ratio of average symbol power to average error power:

MER(dB) = 10log (average symbol power ÷ average error power)

In the case of MER, the higher the number, the better, just as SNR. Every point in a given QAM constellation has a fixed assigned location. If the constellation point deviates from the assigned location, indicating system degradation, then the MER will be a low number (see Table 1).

Table 1. Acceptable MER values for different types of QAM constellation

For digitally modulated signals, ACP is usually the ratio of the power in the main channel to the power in an adjacent channel. If the modulation is digital, the main channel will have noise-like statistics. Whether the signals in the adjacent channel are due to broadband noise, phase noise, or intermodulation of noise-like signals in the main channel, the adjacent channel will have noise-like statistics. One of the goals of the DOCSIS’s DRFI specification is to provide the minimum intended analog channel CNR protection of 60 dB for systems deploying up to 119 QAM channels. The specification assumes that the transmitted power level of the digital channels will be 6 dB below the peak envelope power of the visual signal of analog channels, which is the typical condition for 256 QAM transmissions. Table 2 shows the ACP requirement for any modulated QAM channel within the allocated RF bandwidth based on the DOCSIS® Specifications – Downstream RFI (DRFI) Interface.

Table 2. The actual measured ACP for an 8-channel QAM reference design

The availability of direct RF synthesis DACs, together with multiplier blocks, memory and logic element rich Stratix IV FPGAs create a perfect, all-digital modulator for the next generation of edge QAM solutions. The DSP Builder Advanced Blockset with MATLAB design environment allows engineers to build a system from scratch in a quick and easy manner.

Conclusion

About the Author: Tam Do, Senior Technical Marketing Manager, Broadcast/Automotive/Consumer Business Unit

As senior technical marketing manager of the Broadcast/Consumer Applications Business Unit, Tam Do is responsible for all technical and marketing issues related to the digital broadcast, automotive, and consumer electronics industries. Mr. Do joined Altera in June 2003. Before that time, he was most recently the application design manager of LSI Logic’s Consumer Product Group, where he focused on the development design of an ASSP evaluation system and software for the set-top box industry. Mr. Do holds a BSEE from the University of Nevada Reno, and has close to 20 years of electronics system experience with LSI Logic, Stratex Network, and Verizon Corporation.