Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
This application note describes two reference designs that demonstrate Ethernet operations of the Altera® Triple-Speed Ethernet MegaCore®functions with on-board Marvell 88E1111 PHY chips. The reference designs provide flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopbacks.
The reference designs are Qsys systems integrating one instance of the Triple-Speed Ethernet IP Core that supports 10/100/1000-Mbps Ethernet operation. One reference design runs in the Arria® II GX FPGA … Read More → "Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design"

