This application note describes two reference designs that demonstrate Ethernet operations of the Altera® Triple-Speed Ethernet MegaCore®functions with on-board Marvell 88E1111 PHY chips. The reference designs provide flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopbacks.

The reference designs are Qsys systems integrating one instance of the Triple-Speed Ethernet IP Core that supports 10/100/1000-Mbps Ethernet operation. One reference design runs in the Arria® II GX FPGA development board and integrates one instance of the media access controller (MAC) function. The Triple-Speed Ethernet IP core connects to the on-board PHY chip through Reduced Gigabit Media Independent Interface (RGMII).

The other reference design runs in the Stratix® IV GX FPGA development board and integrates one instance of the MAC with physical coding sublayer (PCS) and physical medium attachment (PMA) functions. The Triple-Speed Ethernet IP core connects to the on-board PHY chip through Serial Gigabit Media Independent Interface (SGMII) mode.