Articles – Page 253

SoC FPGA ARM Cortex-A9 MPCore Processor Advance Information Brief

October 11, 2011

This document describes the dual-core ARM® Cortex™-A9 MPCore™ processor integrated in the hard processor system (HPS) of the Altera Cyclone® V and Arria® V SoC FPGAs. This innovative HPS contains a microprocessor unit (MPU) with a dual-core ARM Cortex-A9 MPCore 32-bit application-class processor, memory controllers, and a rich set of system peripherals, hardened in Altera’s most advanced 28-nm FPGA fabric. These SoC FPGAs provide the performance, power, and cost savings of hard logic, with the flexibility and time-to-market benefits of programmable logic.

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SoC FPGA Product Overview Advance Information Brief

by Amelia Dalton

October 11, 2011

Altera’s 28-nm Cyclone® V and Arria® V SoC FPGAs feature a hard processor system (HPS) containing a microprocessor unit (MPU) with a dual-core ARM® Cortex™-A9 MPCore™ processor, a rich set of peripherals, a multi-port memory controller, and FPGA fabric. The tight integration between the HPS and FPGA fabric supports over 100-Gbps peak bandwidth with integrated data coherency between the processors and the FPGA. The included set of hardened embedded peripherals eliminates the need to implement these functions in programmable logic, leaving more FPGA resources for … Read More → "SoC FPGA Product Overview Advance Information Brief"

Practical Use of FPGAs and IP in DO-254 Compliant Systems

by Kevin Morris

October 11, 2011

This whitepaper is meant to open discussion on these topics, but it is not to be construed as official guidance regarding DO-254 application to IP cores or systems on chips. Similar topics are the subject of the joint US and European DO-254 User Group papers, which are directed to influence policy making in both of these subject areas. The methods that are presented in this white paper should be discussed with the appropriate avionics certification personnel prior to application on any avionics … Read More → "Practical Use of FPGAs and IP in DO-254 Compliant Systems"

Shaking Up Embedded Processing

Altera Introduces SoC FPGAs

by Kevin Morris

October 11, 2011

There is no question that programmability is the key enabling feature of just about every electronic product today. If you’re a regular reader of this publication, and you’re designing systems that don’t contain programmable elements, what the heck are you doing.

We are all very familiar with software programmability. From communications infrastructure to digital cameras, we are constantly hearing that software development is the critical path in the schedule, the biggest engineering effort, and the key element of product differentiation. However, the pace of development today is making hardware programmability equally … Read More → "Shaking Up Embedded Processing"

High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design

by Jim Turley

October 10, 2011

The rapid change in today’s design environment requires a programmable solution that provides the highest performance and lowest power at the lowest cost. To meet the needs of high-volume systems, it isessential that the solution uses the latest 45nm high-volume technology.

The purpose of this whitepaper is to describe how Spartan®-6 FPGAs address the needs of high-volume systems. The ability to connect efficiently and inexpensively to commodity memories, high performance chip-to-chip interface capability, and innovative power down modes arejust a few … Read More → "High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design"

Hi-Tech Spark Arrestor

by Bryon Moyer

October 10, 2011

Hoover Dam is pretty damn impressive. Why, some might simply say it’s a pretty dam.

As you take the tour, much is said about its size, the effort to build it, the clever techniques used to cool the concrete, and, if you’re lucky, the volume of water rumbling through the penstocks inches below the ominously vibrating surface you’re standing on.

But even before you get to the tour, there’s another inescapable feature. Assuming you park at the south end and walk back towards the dam, you have … Read More → "Hi-Tech Spark Arrestor"

DO-254 for the FPGA Designer

by Kevin Morris

October 6, 2011

The standard that governs the design of avionic components and systems, DO-254, is one of the most poorly understood but widely applicable standards in the avionic industry. While information on the general aspects of the standard is easy to obtain, the details of exactly how to implement the standard are sketchy. And once an entity develops a process that achieves compliance, the details of how compliance was achieved become part of the intellectual property of that entity. This white paper focuses on … Read More → "DO-254 for the FPGA Designer"

Engineering an Experience

The Legacy of Steve Jobs

by Kevin Morris

October 6, 2011

In 1976, when Apple Computer was launched, I was in high school. A year later, when the company launched the Apple II – my soul was drawn to the device. For me, it embodied the promise of a new future, where intelligent machines blended functionally and aesthetically into our lives, changing the very meaning of humanity itself. For me, the Apple II was not so much a device as a piece of art and inspiration – a window into the future.

That’s because I was both a hard-core nerd and a sappy teenager at … Read More → "Engineering an Experience"

Considerations Surrounding Single Event Effects in FPGAs, ASICs, and Processors

by Bryon Moyer

October 5, 2011

All sub-micron integrated electronics devices are susceptible to SEEs to some degree. The effects can range from transients causing logical errors, to upsets changing data, to destructive soft error latch-up (SEL). Traditionally, FPGAs were targeted as being more sensitive due to their use of SRAM for the configuration storage. As dimensions shrink to below 90 nm, SEEs in all devices (ASICs, ASSPs, and FPGAs) must be considered.

While targeted to an avionics audience, this white paper has broad applicability to … Read More → "Considerations Surrounding Single Event Effects in FPGAs, ASICs, and Processors"

Developing Tamper Resistant Designs with Xilinx Virtex-6 and 7 Series FPGAs

by Bryon Moyer

October 5, 2011

This application note provides anti-tamper (AT) guidance and practical examples to help the FPGA designer protect the intellectual property (IP) and sensitive data that might exist in an FPGA-enabled system. This protection (in the form of tamper resistance) needs to be effective before, during, and after the FPGA has been configured by a bitstream. Sensitive data can include the configuration data that sets up the functionality of the FPGA logic, critical data and/or parameters that might be included in the bitstream (e.g., initial block RAM … Read More → "Developing Tamper Resistant Designs with Xilinx Virtex-6 and 7 Series FPGAs"