All sub-micron integrated electronics devices are susceptible to SEEs to some degree. The effects can range from transients causing logical errors, to upsets changing data, to destructive soft error latch-up (SEL). Traditionally, FPGAs were targeted as being more sensitive due to their use of SRAM for the configuration storage. As dimensions shrink to below 90 nm, SEEs in all devices (ASICs, ASSPs, and FPGAs) must be considered.

While targeted to an avionics audience, this white paper has broad applicability to any industry where safety and reliability are of critical importance. It should be useful to a wide audience comprised of system architects, engineering and program managers, and certification authorities. Some knowledge of programmable or custom devices, with or without microprocessors, and associated design methodologies is assumed.