Articles – Page 246

December 20, 2011

I’m going to throw a hypothesis out there: In any large engineering team, 99% of the work is done by 1% of the engineers.

There, I said it. It’s like the 80/20 rule, but I assert that 80/20 is far too generous for most engineering squads. We can debate whether it’s 85/15, or 90/10, or – heck, I guess the total doesn’t have to be 100. I’d say 90% of the engineering work could be done by 1% of the engineers. 80/20 is just a confusing breakdown of convenience.

I was talking with an owner of … Read More → "Understanding the 99%"

New Module Triples TESEQ Digital Receiver EMC Testing Range to 18 GHz Fully compliant with CISPR 16-1-1 and MIL-STD

by Amelia Dalton

December 19, 2011

TESEQ, a leading developer and provider of instrumentation and systems for EMC emission and immunity testing, now offers a high-performance digital EMC/EMI receiver module that extends the frequency range of the PMM 9010 receiver system from 6 GHz to 18 GHz. Ideal for use in commercial test labs and by in-house manufacturers’ test facilities, the upgraded PMM system can now be used for a wider range of EMC testing.

The innovative PMM 9180 offers high performance, convenience and cost savings by cutting turnaround times and eliminating the need for expensive coax cables and periodic calibration checks. It … Read More → "New Module Triples TESEQ Digital Receiver EMC Testing Range to 18 GHz Fully compliant with CISPR 16-1-1 and MIL-STD"

The MEMS Testing Quagmire

Players are Increasingly Looking for Extrication

by Bryon Moyer

December 19, 2011

Testing is an unfortunate but important requirement for being in the chip business. Unfortunate because it’s expensive and, well, annoying. Important because no one would trust electronics that had never been tested. And systems builders would end up throwing a lot of useless stuff away. It’s the “failure costs 10x as much for each later stage at which it’s caught” thing.

When we test standard digital ICs, we have two places to catch problems. At the wafer level, we can probe and run some tests to ensure that we … Read More → "The MEMS Testing Quagmire"

Bashing Bugs

by Dick Selwood

December 15, 2011

Horrendous quote of the day – “27% of the industry requires 3 or more spins.” This is the headline on a slide from Harry Foster, of Mentor, based on a large worldwide survey of silicon and FPGA implementers and their verification problems, conducted by Wilson Research in 2010. OK, the positive side is that 73% get it right by second spin, and a further 23% by the fourth time round. But with spins costing multiple millions of dollars, you have to have a huge market for a chip to justify that number of spins, and a market that is prepared … Read More → "Bashing Bugs"

Smart Meters and Dumb Users

Silicon Labs’ New 8051 Chips May Run Afoul of Luddites

by Jim Turley

December 14, 2011

When I was a kid, the garbage men would come into our backyard. Every week they’d park the big truck out front, hop down from the cab, let themselves in through the side gate, and walk around back to where our round metal garbage can waited on the porch outside the kitchen door. One burly man would hoist the can onto his shoulder; if we filled two cans that week, they’d both carry one. They’d retrace their steps, dump everything into the back of their big truck and make a final round trip … Read More → "Smart Meters and Dumb Users"

Silicon Symbiosis

Lattice Acquires SiliconBlue

by Kevin Morris

December 13, 2011

Anyone who watches the programmable logic industry has seen a major resurgence from Lattice Semiconductor over the past couple of years. Just a few years ago, the company was on the ropes financially and technically, and many experts were expecting the company to quietly perish in the night.

It did not.

Instead, Lattice came back with a spark of focused determination seldom seen in long-lived technology companies. The executive ranks were purged and refilled, the culture was dramatically transformed – from a rigid, top-down dictatorship to a bottom-up, participative, team-oriented environment that fosters creativity and … Read More → "Silicon Symbiosis"

Magnetic Momentum

Crocus Sees Big Things in Their New MLU Technology

by Bryon Moyer

December 12, 2011

We think of logic as an electrical phenomenon. In the past, memory was a magnetic domain, then it shifted to electronic, and, with the further development of MRAMs, it’s coming back around to magnetic again.

Crocus has been riffing off of their magnetics to the point where their MLU technology has some potential to make inroads not only into memory electronics, but even into logic. They’ve been … Read More → "Magnetic Momentum"

Optimizing 10-Gbps Backplane Performance on Stratix V FPGAs

by Amelia Dalton

December 8, 2011

With our Transceiver Signal Integrity Development Kit, Stratix V GX Edition and the Transceiver Toolkit tool in Quartus II software, you can easily and efficiently evaluate the performance of the high-speed serial transceivers in the Stratix V FPGA.

Watch this 7-minute video to:

See a 10GBASE-KR backplane demo using the Transceiver Signal Integrity Development Kit, Stratix V GX Edition
Learn how to use Transceiver … Read More → "Optimizing 10-Gbps Backplane Performance on Stratix V FPGAs"

Cheap as Chips?

by Dick Selwood

December 8, 2011

How do you get from an idea to an ASIC? Classically you shell out multiple dollars for a design tool-chain, and many more dollars for people to drive it. After a lengthy period of definition, design, and verification, you send data to a foundry, pay many more millions of dollars for a mask set, and get back, weeks later, a box of wafers. Now you spend even more money on probing the wafers, and, if you are lucky/skilled, you have a working device and can move into production – that is, after putting together a logistic chain for … Read More → "Cheap as Chips?"

The Process of FPGA Design Takes Giant Leap Forward With the New Stellar IP Tool from 4DSP

by Amelia Dalton

December 8, 2011

4DSP LLC takes another giant leap forward in simplifying the process of FPGA design by releasing their new Stellar IP tool. Stellar IP is designed to automate the creation of an FPGA image by reusing proven IP cores. It offers a platform for software engineers to target FPGA devices.

In recent years, the substantial growth of resources available inside FPGA devices has forced engineers to change the way they approach programmable logic design. A higher level of abstraction and the removal of error prone tasks are critical to the success and timely completion of projects. FPGA technology … Read More → "The Process of FPGA Design Takes Giant Leap Forward With the New Stellar IP Tool from 4DSP"