Optimizing 10-Gbps Backplane Performance on Stratix V FPGAs

by Amelia Dalton

With our Transceiver Signal Integrity Development Kit, Stratix V GX Edition and the Transceiver Toolkit tool in Quartus II software, you can easily and efficiently evaluate the performance of the high-speed serial transceivers in the Stratix V FPGA.

Watch this 7-minute video to:

See a 10GBASE-KR backplane demo using the Transceiver Signal Integrity Development Kit, Stratix V GX Edition
Learn how to use Transceiver Toolkit to observe and improve link performance
See the effects of signal conditioning on the receiver’s margin using Altera’s EyeQ tool

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Peak Power Introduction and Solutions

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In this episode of Chalk Talk, Amelia Dalton and Karim Bheiry from MEAN WELL explore why motors and capacitors need peak current during startup, the parameters to keep in mind when choosing your next power supply for these kind of designs, and the specific applications where MEAN WELL’s enclosed power supplies with peak power would bring the most benefit.

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Jan 22, 2024

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Optimizing 10-Gbps Backplane Performance on Stratix V FPGAs

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