Articles – Page 206

November 18, 2013

Here’s one possible way to not get a job. Let’s say the interviewer asks you about things inside a cell phone. And you, having an FPGA background, suggest that there’s an opportunity for some great FPGA usage inside said phone.

Yeah… you’re likely to get a polite, “That’s interesting…” and a note, “FPGA guy with an FPGA hammer… and every system is his nail, even if it has a Philips head on it… Pass…”

No one puts baby in the corner, and no one puts FPGAs in phones or small … Read More → "FPGA Fone Fusion"

Art Majors vs. Programmers

Express Logic GUIX Brings Graphics to Embedded Interfaces

by Jim Turley

November 13, 2013

Maybe it’s a left-brain/right-brain thing. Programmers usually aren’t very good user-interface designers. Drawing all those windows, buttons, and scroll bars gives most developers the willies.

Enter GUIX, a new GUI-design tool from Express Logic, the people who make the ThreadX real-time operating system. GUIX brings lightweight GUI widgets to smallish embedded systems, allowing programmers to stick to their programming and leave the GUI gooeyness to the liberal-arts majors.

Astute followers of Express Logic’s oeuvre may be thinking right now, “Wait a minute… don’t those guys already … Read More → "Art Majors vs. Programmers"

FPGAs Ready-to-Eat

QuickLogic Does the Cooking For You

by Kevin Morris

November 12, 2013

The FPGA market is a wasteland – littered with the battered corpses of startup companies who thought they could build a better mousetrap. They attacked the strongholds of market leaders Xilinx and Altera and ended up paying the ultimate price. But none of these entrepreneurs were dummies. In fact, in just about every case they had a novel idea that brought significant advantages to the programmable logic designer.

The reason they failed, however, was remarkably consistent. It wasn’t because they had inferior chips. In fact, they often had devices with improved capabilities for … Read More → "FPGAs Ready-to-Eat"

3D IC Testing and Yields

Imec/Delft Tool Manages Tradeoffs

by Bryon Moyer

November 11, 2013

It used to be pretty straightforward to figure out the cost of a finished IC. You had a linear progression of steps, each of which cost something to perform, and each of which might cause some fallout. In the end, your die cost was simply the sum total of all of those steps amortized over however many dice survived the whole process.

We’ll call creating a wafer a single step, even though, obviously, it’s enormously complex – and getting more so by the hour. But some number of the chips on the wafer (hopefully a lot) … Read More → "3D IC Testing and Yields"

Mystery CPU for the Masses

New Synopsys Processor Makes Leaps in Performance

by Jim Turley

November 6, 2013

Pop quiz! What’s the second-most-popular CPU core in the world? First place goes to ARM, of course, but who’s the runner-up?

If you guessed MIPS, PowerPC, x86, Tensilica, 8051, or XMOS, you’re wrong. (In good company, but still wrong.) The correct answer is: ARC.

According to Synopsys, 1.3 billion ARC processors were embedded into chips last year, and that number is growing by about 300 million per year. That puts ARC second only to the mighty ARM. Must be something about the name. Maybe all those designers thought they were getting ARM but … Read More → "Mystery CPU for the Masses"

The Hard Ceiling

Power Plays the Death Card

by Kevin Morris

November 5, 2013

Moore’s Law is a maddening mistress. As our engineering community has collectively held the tail of this comet for the past forty-seven years, we’ve desperately struggled to divine its limits. Where and why will it all end? Will lithography run out of gas, brining the exponential curve of semiconductor progress to a halt? Will packaging and IO constraints become so tight that more transistors would make no difference? Or, will economics bring the whole house of cards crashing down – putting us in a situation where there is just no profit in pushing the process envelope?</ … Read More → "The Hard Ceiling"

Taking Sensors to a Trillion

TSensors Conference Targets a Roadmap

by Bryon Moyer

November 4, 2013

You’ve probably all attended one of these meetings. A high-ranking person in an organization wants to make a strategic change or raise the priority of some neglected issue or otherwise alter how things work. But in a post-Dickensian world, he (yes, it could be a “she,” although, as yet, it largely isn’t in our overwhelmingly male industry, and the “he-ness” has implications) can’t just legislate by fiat.

No, he must call a meeting with at least one level of lieutenants below him. And, together, they’re supposed to have a reasoned conversation that yields … Read More → "Taking Sensors to a Trillion"

Demystifying CPC

A Click By Any Other Name Would Sound As Sweet...

by Kevin Morris

November 4, 2013

With apologies to Shakespeare, online marketers have been swamped with metrics over the past couple of decades. With the alphabet soup of online marketing – CPC, CPI, CPM, CPA, CTR… (the list goes on and on – and that’s just the “C”s) it’s no wonder that marketers are confused.

One metric that many can relate to easily is the “click.” Sounds simple, right? You put a thing on the web, somebody clicks on it – BAM! That’s One. OK, now we can count them – two, three, four – Hey, this is FUN!

Next, we can … Read More → "Demystifying CPC"

A Look Into How a High-Level Synthesis Design Flow Benefits Verification Turnaround

by Jim Turley

October 31, 2013

Introduction

The design and re-use productivity benefits of SystemC-based high-level-synthesis (HLS) are generally well understood. However, a major benefit of moving to this level of design that is rarely explored is improved verification turnaround and productivity.

Most system-on-chip (SoC) design flows employ SystemC transaction-level models (TLM) to create virtual prototypes. These virtual prototypes are used to verify the ever-increasing degree of software content. The utilization of SystemC models in the design flow forms an approach that Jim Ready, Cadence’s chief technology advisor for software and embedded systems, refers to as “software-driven SoC … Read More → "A Look Into How a High-Level Synthesis Design Flow Benefits Verification Turnaround"

It’s Raining MCUs Over Texas

TI’s ’C129 Chips Connect GUI to the Cloud

by Jim Turley

October 30, 2013

Texans know clouds. Whether he’s a rancher or a farmer, your basic Texas agriculturalist makes his living looking at the sky and knowing which way the wind blows. And in Texas, it blows a lot. (Trivia: You can tell a rancher from a farmer by his hat. Ranchers wear cowboy hats; farmers wear ball caps.)

And that ol’ Texas wind is blowing clouds right up into Dallas, home of Texas Instruments. The clouds have blown through the marketing department and straight into engineering. And after stirring up a little dust, out blows a new MCU family.</ … Read More → "It’s Raining MCUs Over Texas"