Three decades ago – at the dawn of programmable logic technology – programmable logic devices such as CPLDs and FPGAs were primarily used for “glue logic.” That is, they could connect just about any digital thing to any other digital thing, regardless of the interface or protocol. In simple terms, FPGAs were digital duct tape.
Those times are long gone, however, with today’s fancy feature-packed devices brimming with memories and multipliers and processors and AI engines, design teams are using FPGAs as full-fledged systems-on-chip (or -in-package). But one of the key features of FPGAs continues to be the rich and robust selection of external interfaces and the ability to bridge between those with flexible programmable LUT fabric.
Well, perhaps those days aren’t quite so “gone” after all.
Lattice Semiconductor recently announced CrossLinkPlus – an updated and aptly-named iteration of their popular “CrossLink” devices, which are the modern-day embodiment of “glue logic,” connecting many lanes of MIPI to just about any interface and protocol you’d want. There is a host of peripherals out there that you’d love to connect to your SoC, but with all of them speaking different protocols and using different IO standards, it’s really difficult to match up your SoC with your sensors, displays, and other widgets. Sometimes, even if your SoC has the right interface, you’ve got too many devices to connect to that port type, and you can end up designing in a larger, more expensive, more power-hungry application processor than you need – just to get the IO you require.
CrossLinkPlus gives you a better way to do all that. You can use it to connect multiple sensors, multiple/different displays and display types, and just about any interface or protocol that you can name into your system. CrossLinkPlus supports SubLVDS, LVDS, SLVS200, CMOS, and MIPI D-PHY. The magic is in the MIPI side – as the device packs two four-lane MIPI D-PHY transceivers at 6Gbps per port – giving a total of 12Gbps on the MIPI side and 11 programmable, source-synchronous I/O pairs for camera and display interfacing. It brings along 6K LUTs of FPGA fabric – enough for some pretty fancy bridging interconnect – as well as 180Kb embedded memory. It’s like an old-school glue logic FPGA, but with modern interfaces. It packs all this into a tiny 3.5mm X 3.5mm package, and it burns a miserly 5 mW – 135 mW operating power.
As those in the front of the room may have already noticed, there is a “Plus” on the end of “CrossLinkPlus.” That’s because Lattice has been selling the CrossLink family for a while:
The “Plus” turns out to be a biggie. Lattice has added on-chip flash configuration memory to the CrossLink device. That means several good things. First, you don’t have to add off-chip FPGA configuration stuff to your design. Second, and most importantly, you can load the configuration bitstream into the device from on-chip flash in less than 10ms. That makes the FPGA qualify as “instant on.” 10ms is important because the human brain is able to perceive images after 15ms, so power-up and configuration can happen faster than human perception – hence, “instant on.”
For many of the applications of this device – smart cameras, IoT devices with varying displays, etc. – that rapid startup means that more of the device can be left in “sleep” mode – which saves the most valuable commodity of all – system power. If your system can be largely powered down during vast standby intervals and can be instantly summoned to life to begin useful work in the literal blink of an eye, the ever-critical power metrics such as battery life can be extended dramatically.
We expect that this device will co-exist well in systems that also use Lattice’s line of endpoint AI acceleration devices. With the current explosion in AI- and video-driven IoT endpoints with embedded vision intelligence, Lattice is making smart bets on socket wins with their FPGA technology, and they are hitting market holes that large FPGA companies like Xilinx and Intel are largely leaving behind. It will be interesting to watch as this new, low-power, high-performance market for mobile-friendly FPGAs shapes up.