Efinix has just done designers a solid. The company’s new Ti180J484D1 FPGA incorporates a 2Gbit LPDDR4X SDRAM die co-packaged with the FPGA die, which creates a System in Package (SiP) device that results in a smaller footprint on your circuit board. In addition, you won’t need to worry about the precise pcb trace-length matching that’s required to properly connect the DDR SDRAM to the FPGA. Efinix has handled that for you already. The idea’s similar to those high-end FPGAs from other vendors that package HBM (high-bandwidth memory) DRAM stacks with the FPGA, including some Altera Agilex 7 devices (see “Intel Announces World’s Fastest FPGAs with in-package HBM: The Intel Agilex M-Series FPGAs”), which only just started shipping, and some AMD Versal and Virtex UltraScale+ devices. However, the LPDDR4X SDRAM that Efinix is using in the Ti180J484D1 FPGA is a lot slower than HBM DRAM, and Efinix’s SiP devices should be a lot less expensive as well. 

The Efinix Ti180J484D1 FPGA co-packages an FPGA die and an LPDDR4X SDRAM die to create a space-efficient System in Package (SiP) device. Image credit: Efinix

This Ti180 FPGA is available packaged with only one size of SDRAM die and in only one package, the J484D1 FBGA (Fine-pitch Ball Grid Array), which measures 15x15mm with a 0.65mm ball pitch. Because the packaged Ti180J484D1 FPGA needs no external pins to communicate with a separate SDRAM chip, the device has 190 high-speed I/O pins, compared to 116 I/O pins available in the standard Ti180J484 FPGA package. The Ti180J484D1 FPGA’s in-package LPDDR4X SDRAM communicates with the FPGA’s hardened, on-chip LPDDR4/4X memory controller at 3000 Mtransfers/sec over a 16-bit data bus.

The Ti180 FPGA die in the Ti180J484D1 SiP is the same FPGA die in the Ti180J484 FPGA. It’s equipped with 176,256 logic elements, 13.11 Mbits of embedded SRAM organized as 1280 10Kbit memory blocks, and 640 DSP blocks. The FPGA’s logic elements are housed in Efinix’s claim to fame: the XLR (eXchangeable Logic and Routing) cell, which combines the FPGA’s programmable logic (including a fractionable 4-input LUT, an adder, and a register that can also serve as a shift register) and routing resources in one block. Efinix claims that the XLR cell provides better cell utilization than other vendors’ FPGA architectures that segregate the logic from the routing. Your mileage may vary, so you really need to compile and test-fit your design into an Efinix FPGA to validate the company’s claim.

The FPGA’s 10Kbit SRAM blocks can operate as single-port, simple dual-port, or true dual-port RAM and can function as ROM by initializing the memory content during FPGA configuration. The SRAM block’s read and write port widths can be independently configured, and the simple dual-port mode supports a write byte enable. The company’s Efinity design software can cascade memory blocks automatically to create wider and deeper memory arrays.

Efinix’s fractionable DSP blocks consist of one 19×18-bit integer multiplier with 48-bit addition or subtraction. Each block can be split into one 11×10-bit integer multiplier and one 8×8-bit integer multiplier with two 24-bit add/subtract units or one 7×6-bit integer multiplier and three 4×4-bit integer multipliers with four 12-bit add/subtract units. You can also configure the DSP block as a fused BFLOAT16 multiplier/adder/subtractor. Ti180 FPGAs also include multiple, hardened MIPI D-PHY blocks that you can use with soft MIPI CSI-2 and DSI controller IP cores to create multi-camera vision systems with hardware acceleration.

The new Ti180J484D1 FPGA is not Efinix’s first venture into SiP. The company already offers the Ti60 F100 FPGA, which co-packages a Titanium Ti60 FPGA with 256 Mbits of SRAM and a 16Mbit SPI NOR Flash EEPROM to create a MIPI-centric chip for vision systems or other sensor aggregation applications.

Because Efinix chose to co-package the Ti180 member of its Titanium FPGA family with SDRAM, it’s interesting to see what you don’t get in the Ti180J484D1 FPGA. You don’t get high-speed SerDes transceivers, Ethernet MACs, PCIe controllers, or multi-core RISC-V processors. However, Efinix has put high-speed transceivers and some hardened cores such as a PCIe Gen4 controller and a quad-core RISC-V processor into other members of the Titanium FPGA family.

The company also offers soft-core versions of other IP blocks like a 10G Ethernet MAC. In case you feel the urge to configure a processor with custom instructions, Efinix also offers a soft-core processor called Sapphire that’s also based on the RISC-V ISA. You can read about the design flow for creating such a processor in the Efinix blog titled “RISC-V and Custom Instruction Acceleration on Efinix FPGAs.” Just be aware that processors implemented as soft cores and instantiated into FPGAs always run at lower clock rates than hardened processor cores implemented in the same semiconductor process technology. They’re roughly an order of magnitude slower. That’s not a characteristic that’s unique to processor IP. All IP cores will run more slowly when instantiated into an FPGA’s programmable logic. It’s the nature of the beast and goes with the territory.

Currently, there are ten members of the Efinix Titanium FPGA family available, ranging from 36K to 370K LEs. Three larger members with 550K, 750K, and 1M LEs are currently under development. The Ti180J484D1 and TI60F100 devices are the two SiP parts in the Titanium family, to date. I contacted Efinix’s VP of Marketing Mark Oliver to ask about the Ti180J484D1 FPGA and about possible future SiP products based on other members of the company’s Titanium FPGA family. Oliver replied:

“We already have the Ti60F100 with both Flash and Hyper-RAM. That device has been very popular and prompted us to extend the offering to the Ti180 size. SiP packages are something we will continue to do since they are popular with our customer base. Unfortunately, there seem to be as many requested configurations as there are customers so it’s a little tricky to select the right sweet spot. We don’t have any concrete plans for more devices at this point but I’m sure we will extend the line.”

For more information about the Efinix line of Titanium FPGAs, see “A Deeper Dive into Efinix with VP of Marketing Mark Oliver.”

Reference

Efinix White Paper, “Why the XLR Cell Is a Big Deal.”