The FPGA community is tiny. You can count the number of FPGA vendors on one hand, if you neglect to count the three or four vendors in China who are dedicated to their domestic market. Anyone familiar with the FPGA market can likely name AMD (the FPGA company formerly known as Xilinx), Altera (the FPGA company formerly known as Intel PSG, which itself was previously known as Altera), Lattice Semiconductor, and Microchip (which fell into the FPGA market by buying Microsemi, the original purchaser of FPGA maker Actel). If you’re a real student of the FPGA market, you might have heard of Efinix (pronounced “eff-finix”), a small FPGA vendor headquartered in Cupertino, California, which was founded in 2012 by Altera alums Sammy Cheung and Tony Ngai. I was at least aware of Efinix, but I had not succeeded in communicating with the company. When the company’s VP of marketing Mark Oliver commented on my recent FPGA Awards article (see “The First Annual FPGA Awards – the Fibbies – celebrating 40 years of FPGAs”), I jumped on the chance to learn more about this FPGA company. After Oliver finally found my emails in his spam folder, he and I scheduled an interview for early February.
First, Oliver provided Efinix’s origin story:
“We started about 12 years ago. The two founders of the company, Sammy Chung and Tony Ngai, were both at Altera. Sammy was responsible for Altera’s HardCopy initiative. They looked at what Altera was doing, and the way FPGAs were going, and they said to themselves, ‘You know what? Knowing what we know about the FPGA industry and what customers are going to need going forward, FPGAs are not going to be it because they’re getting more power hungry, they’re getting bigger, and they’re getting more expensive. We see systems moving towards the edge and out of the data center over time. FPGAs are moving in the opposite direction.’”
Chung and Ngai had noticed Xilinx’s and Altera’s increasing focus on high-end FPGAs, at the expense of mid-range and low-end FPGAs. This is the trend that Lattice spotted and exploited to its own benefit. Oliver continued:
“So, they said time out. Let’s start over and do better FPGAs so that they can be everything that they’re supposed to be: fast time to market, prototype to mass production, low power, and cheap, but ultimately versatile and efficient platforms. So, they started Efinix and spent eight years or so perfecting the XLR cell, the ‘exchangeable logic and routing’ cell [that’s at the heart of Efinix FPGAs]…
The Efinix XLR cell operates as a logic element or as a routing element. In certain cases, it can be both. Image credit: Efinix
“We say that the XLR cell can be used either as logic or routing, but in reality it’s logic and routing, depending on what you’re putting into the logic cell. We stamp these XLR cells all over the [FPGA] die, so… you end up with a simple FPGA. The XLR cell uses standard CMOS [manufacturing] technology. If you need routing, you use them [the XLR cells] as routing. If you need extra logic, you use them as logic. So, you end up with 100% utilization, or something close to that.
“Occasionally, it’s actually greater than 100% utilization… We slightly overprovision the FPGAs just in case your designs are wacky and don’t quite fit perfectly. There are cases when that’s true. If [your design fills the FPGA] and we’ve still got overprovisioned [XLR cells] left over, we’ll let you use them. We have customers out in the real world that are using greater than 100% of our FPGAs.”
The Trion family, manufactured by SMIC, became Efinix’s first FPGA product line. Development of the XLR cell meant that Efinix could greatly reduce the need for routing tracks and it enable the use of conventional CMOS processing, with many fewer metal layers than are needed by high-end FPGAs. Trion FPGAs are built on SMIC’s 40nm planar process technology and have a logic density range of 4K to 120K logic elements (LEs). To me, members of the Trion family look like a return to the FPGA architecture of the 1990s or the early 2000s. They incorporate on-board programmable logic, embedded memory blocks, 18×18-bit multipliers, a variety of simple I/O ports, and embedded memory controllers for DDR3, LPDDR3, and LPDDR2 SDRAMs. What’s missing from these first Efinix FPGAs are high-speed SerDes transceivers and hardened IP blocks such as PCIe controllers and microprocessor cores.
Oliver then described Efinix’s next steps in its evolutionary path:
“When we looked at what we learned from Trion, we rearchitected the XLR cell slightly to make our follow-on Titanium FPGA products. We added registers in the XLR cell to make it a little bit more complex, but it’s essentially the same cell. We designed a much better DSP [with 19×18-bit integer multiplication and 48-bit addition/subtraction] that’s more capable of executing tasks like AI. The DSP is fracturable and does much better math, so it’s more efficient.
“Titanium FPGAs are built in a 16nm process by TSMC, so we moved fabrication out of China and into Taiwan. Because Titanium FPGAs are 16nm devices, we get a much higher performance and lower operating power. The Trion family is still our workhorse product and is probably 60% or 65% of our revenue, but the Titanium family is getting a lot of the design wins right now, so the product ratio is starting to skew over towards Titanium. Our latest product, the Titanium 375, has high speed SerDes ports, and that’s a 16Gbps SerDes, so the Titanium 375 also has a hardened PCIe Gen4 x4 controller. We’ll be demoing these parts at Embedded World in Germany, in mid-March.”
Efinix announced the Titanium 375 FPGA in 2024 and will be demonstrating it at Embedded World this year. Image credit: Efinix
If you’re wondering where Efinix’s Titanium FPGAs fit in the overall, multivendor hierarchy, Oliver said:
“We go head-to-head with [FPGAs] like [AMD’s] Kintex UltraScale Plus and we pretty much match that performance. Put a similar design in both of our technologies, and we operate at about one-third of the power. So, significantly lower power, better efficiency, and a tiny fraction of the cost.”
One of the soft IP cores that Efinix has been offering to its customers is a configurable RISC-V processor core. The company did a bit of market research and discovered that something like 90% of its customers were putting soft-core microprocessors onto Efinix FPGAs, so the logical next step was to incorporate hardened processor cores in the company’s FPGAs. Several of the FPGAs in the Titanium family have hardened, quad-core RISC-V processors. However, Efinix has taken a unique approach to adding hardened processor cores to its FPGAs, as Oliver explained:
“We split the inner math part of the CPU, including the ALU and registers, away from the peripherals. The peripherals are still configurable in the [programmable logic] fabric because they run at a lower speed… but the math part, the number-crunchy part, is hardened. As a result, we get gigahertz performance out of the processor, instead of the 250 MHz we got from the soft core. So, that gives us a Linux RTOS-capable, quad-core processing element on the FPGA, but it’s tiny, because we only hardened the processor’s inner core. It’s still configurable, with the peripherals that you want on the outside, [implemented] in the fabric.
“The cool thing about our hardened RISC-V implementation is that it has a custom instruction set. Not all of the [RISC-V processor] instructions are defined. There are a couple of instructions left open for the user to define… You’ve got almost unlimited FPGA fabric to implement a custom ALU, for tasks like AI, for example.”
Having spent the best part of a decade marketing configurable processor cores for ASICs as an evangelist at Tensilica, I’m more aware than most of the potential advantages of user-configurable instruction sets, but Oliver was able to provide a concrete example where the blend of a configurable processor core and an FPGA’s programmable logic fabric can provide a significant performance boost:
“One of our customers, for example, is designing augmented reality (AR) night-vision goggles, and they wanted to be able to identify people with the goggles, draw the obligatory green box around the person, and label the box. They couldn’t find a solution that worked anywhere, not even with microcontrollers, which had the low power consumption and the general performance that they wanted but didn’t have the required AI capability for image recognition. This company came to us and said, ‘What can you do for us?’ We spent a week training their AI model on our FPGA and gave them a solution that met their performance and power budget. It took literally a week’s worth of work. So, they went away happy. Our solution took them straight from the lab to volume production with a cost- and power-effective solution.”
Oliver then provided a second concrete example of a system that benefitted from customized instructions for the integrated RISC-V processors in the Titanium FPGAs using Efinix’s implementation of the TinyML machine-learning platform using FPGA-based acceleration:
“We’ve had folks developing conference room speaker systems that have ten to 15 microphones come to us and say, ‘We love the FPGA; the kind of signal processing that you can give us is critical so that we can do beamforming and follow people around the room as they walk up to the whiteboard. So, love all that. We have three different microcontrollers in the system and a whole bunch of other stuff. You’re not touching that, but what can you do with signal processing?’ We came back and said, ‘Well, we can do the signal processing, but we have half the device leftover. So why don’t you give us the three microcontrollers? We’ll stick those in there too. We can run one on the RISC-V [processor] in software, and, by the way, all of that other stuff that you’re mentioning there, show us what that is. We will absorb that too.’ And we did. The customer reduced their bill of materials and managed to almost double the number of microphones that they could put on the system. They increased the performance of their system and reduced time to market because we just absorbed that code from the microcontrollers.”
For similar reasons, Efinix’s FPGAs seem to have found success in the industrial automation and machine-vision markets. Oliver elaborated by describing the learning path of his customers:
“We pretty much own the industrial camera market, because it’s a compelling story for somebody that wants a tiny footprint [on the board], with low power consumption, out on the edge of the network. Everybody would tell us the same story: ‘Number one, we don’t believe you, but if it’s true, I’ll use your FPGA. Give me a dev kit. Let me play with it.’ So, we do [give them a development kit], and six months later, they say, ‘OK, we’re never going back, but it took us a few weeks or a month or so to come up to speed with your tools. Your tools are a little wacky, but once we got used to the tools and started using them, we love them. They’re the way the tools should have been designed in the first place.”
This anecdote prompted me to ask another question. I’d gleaned from user comments on social media sites such as Reddit that users did find Efinix tools to be very different from the FPGA development tools offered by the larger FPGA vendors (Altera, AMD, Lattice, and Microchip). Oliver explained:
“Way back, when Sammy and [Tony] were sitting in a very small closet somewhere defining the original FPGA architecture, they concluded that tools that stitch together the FPGA with its pad ring and all of its I/O to make everything look like one big homogeneous lump is counterproductive because it does away with the flexibility that you have in reusing the internal fabric, if you wanted to embed an FPGA, for example. It ties you to a pad ring, I/Os, and hardened controllers that you don’t necessarily want to lock into from day one. So, they said, ‘Let’s do it the way ASIC designers do this design flow. Let’s talk about the inside of the chip, the fabric in our case, as one entity, and then let’s figure out how we stitch that and the rest of the peripherals into the PCB.’
“So, we have Core Designer and we have I/O Designer, and they talk between themselves. This gives us the flexibility to be able to innovate in the fabric independently of the I/Os, the hardened controllers, the DDR interfaces, the PCIe controller, and everything else that we want to put in there. The users of the tools are able to develop in teams, separately. So, the guy doing the pad ring innovation can talk to the PCB designers and can get that whole system put together. The guy that’s writing the HDL for the core can work independently. Then we stitch the two together by saying this signal goes to this pad.
“If there are complaints out there, it’s because you now have to somewhat manually stitch the core to the pad ring. Some people don’t like doing that, so in the latest iterations of our tools, we’re automating that process somewhat to take away some of that pain. But the folks that can get their head around our approach and have used the tools for a few weeks or months end up really liking that flow because they can isolate the two different design problems and work on them independently. We think that’s a much better way to partition a system, rather than a tool that treats the design as one big glob where you have to consider everything up front.”
Perhaps one reason for the dissimilarity between Efinix’s design tools and those from other FPGA vendors is because Efinix’s tool development is done in conjunction with the University of Toronto. If university-style tool development gives you pause, remember that the Mead-Conway VLSI design methodology grew out of a collaboration between Carver Mead at CalTech and Lynn Conway at Xerox PARC in the late 1970s, and this methodology continues to shape the way we design ASICs and ASSPs. (See “Lynn Conway, 1938-2024: The Computer Architect Who Helped to Revolutionize Digital IC Design.”)
Finally, I asked Oliver about Efinix’s plans. Here, he became somewhat circumspect:
“So, we talked about Trion, which was kind of a proof-of-concept workhorse. Then we talked about Titanium, which is our higher performance 16nm family from TSMC. We started selling Titanium FPGAs, and a bunch of our customers came back to us and said, ‘Love it. Love Titanium. But we don’t necessarily need a PCIe Gen4 x4 [interface] and we don’t want to pay for it. PCIe Gen3 will work just fine. So, we came out with the Topaz family, which sits between Trion and Titanium. Topaz heavily leverages the Titanium architecture, but it’s optimized for cost.
“The Topaz family gives people lower-cost versions of Titanium FPGAs with almost the same performance. Not quite, but almost. And that helps people take their mainstream applications to market with a Topaz family product right out of the box. It doesn’t burden the AR glasses and the industrial cameras with a Titanium cost, but it gives people the performance that they need to take their product to market with an FPGA. That was the goal…
“At some point, I’m not going to tell you when, you’ll see us flesh out that Titanium family with better, more efficient, and higher performance devices. There will be incremental tweaks to the architecture. The more forward-looking folks are saying that 16nm is cool now, but in a few years, it most definitely will not be. So, which of the process nodes is going to be the mainstream node?
“Well, that could be 4, 5, or 7 nm. Which fab is it with? We’ve got folks looking at that, and if you pick one of those, like 5nm, it has the potential to give you something that’s much higher performance, much smaller or lower power, and gives you the opportunity to innovate with some of the advantages of that process node. We have folks looking at a clean sheet of paper, a clean slate.”
Oliver and I concluded the interview there, leaving me with many more questions about the future, and no firm answers, but I’m sure these answers will unfold in the coming years.
