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AMD discontinues CoolRunner and XC9500 CPLDs and Spartan-II and -3 FPGAs. Buy ‘em while you can!

AMD issued an End of Life (EOL) notice for several older CPLDs and FPGAs on January 1. The notice states that AMD will accept final orders for these devices through June 29, 2024. The affected devices include the XC9500XL, CoolRunner, and CoolRunner II CPLDs, and the Spartan-II and Spartan-3 FPGA families. These products are nearly a quarter of a century old and older. AMD added them to its product portfolio when it acquired Xilinx in 2022. It now appears that the company is cleaning house and discontinuing the older PLDs from the Xilinx acquisition.

When ICs like these older Xilinx CPLDs and FPGAs are discontinued, it’s usually for two reasons. First, the discontinued devices are manufactured using old process nodes on fab lines that were fully amortized many years ago. It’s increasingly expensive to maintain the older equipment on these old lines. Eventually, the fabs either want to reclaim the clean room floor space for newer equipment that can manufacture ICs at newer, more profitable process nodes, or they simply shut down the line. The second reason for discontinuing these old ICs is because declining demand no longer warrants keeping a stock of these chips. It’s unlikely that there are any new designs for the programmable logic chips that AMD is discontinuing, so demand will continue to trend toward zero, and responsible companies like AMD will provide a last-time-buy period to support existing system designs that are somehow still being manufactured.

If that’s all there were to this story, it would not merit an article in EEJournal. However, AMD’s EOL notice provides me with a fresh opportunity to look at how these programmable logic devices came to be and allows me to continue documenting the PLD and FPGA histories that I’ve covered in previous EEJournal articles.

Xilinx was founded in early 1984, and Altera was founded six months earlier. Xilinx developed FPGAs based on the ideas of founder Ross Freeman. Altera’s first product was an EPLD (erasable PLD), which grew into an ever-growing line of CPLDs (complex PLDs). From 1984 through 1992, each company stayed on its side of the FPGA/CPLD line and aggressively touted the advantages of their respective programmable logic approaches. Register-intensive designs generally tended to go into Xilinx FPGAs, and faster designs that would require multiple levels of FPGA LUTs but couldn’t afford the extra gate delays ended up going into Altera CPLDs. However, there were many designs that could use either CPLDs or FPGAs.

Altera crossed the CPLD/FPGA line in 1992 by introducing the FLEX 8000 FPGA, which had been in development for more than a year. Xilinx did not know that Altera was about to cross that line into FPGA territory, but by one of those strange coincidences that sometimes occur in the semiconductor industry, Xilinx announced the acquisition of CPLD supplier Plus Logic in early 1992 and converted the acquired company into the Xilinx EPLD (Erasable PLD) division. So, in 1992, both leading programmable logic vendors crossed into each other’s territory, which further intensified the competition between the two companies and spurred even greater levels of innovation.

Xilinx redesigned Plus Logic’s EPLDs for a new “sub-micron” semiconductor process node (probably 0.8μm, given the timeframe and subsequent Xilinx chip announcements) and made some functional enhancements to the CPLDs’ original design. Plus Logic’s HiPER 2010 became the Xilinx XC7236 with 36 macrocells, and the Plus Logic FPGA2020 became the Xilinx XC7272 with 72 macrocells. These EPLDs used the AND/OR macrocell design that MMI had popularized with its bipolar PALs, but Plus Logic’s EPLDs provided more macrocells than did the PALs and they were based on a CMOS process, so they consumed less power than the bipolar PALs and they were erasable, much like the first EPLDs made by Altera nearly a decade earlier.

Erasability might not seem like such a big deal, but I remember designing with MMI’s 16L8 PALs in the early 1980s while I was designing CAD workstations at Cadnetix. I kept a paper cup of programmed PALs on my desk. These one-time-use PALs, now useless, were the result of designs that weren’t right or hardware accommodations to requests by the software team. At the time, MMI’s PALs cost about $10 each, so seeing the paper cup full of PALs was a somewhat painful reminder of all the changes that I’d made to my workstation designs. Altera’s EP300 erasable PLD was too late for my purposes and would have been too slow as well.

At the end of 1995, Xilinx introduced its second-generation EPLD/CPLD, the XC9500, a 5V device based on a 0.6μm CMOS EEPROM process. EPLDs and CPLDs were generally programmed by an external device programmer, but the XC9500 introduced in-system programming (ISP), which allowed system makers to assemble circuit boards with blank CPLDs and then program the device configuration after the board was assembled. The ISP feature allowed board-level designers to create entire product lines using one board design and simplified field upgrades. Xilinx announced the 3.3V XC9500XL EPLD/CPLD based on a 0.35µm CMOS EEPROM process at the end of 1998.

In 1999, Xilinx jumped on the opportunity to buy the existing CoolRunner CPLD product line from Philips Semiconductors at a bargain price. Along with the CPLD purchase, Xilinx hired 45 Philips employees associated with the CoolRunner product. This product line included 5V and 3.3V devices with densities ranging from 32 to 960 macrocells. The original CoolRunner CPLD family was based on a 0.35μm CMOS EEPROM process. Three years later, in 2002, Xilinx introduced the cost reduced CoolRunner II device family that could run on supply voltages ranging from 1.8 to 3.3V. CoolRunner II CPLDs had 32 to 512 macrocells and were based on a 0.18μm (180nm) CMOS EEPROM process.

Spartan FPGAs are Xilinx’s “cost effective” PLDs. In other words, they’re cheaper than the company’s other FPGA families. The company developed this low-end FPGA product line because its mainstream FPGAs were getting larger and larger, which meant that each new generation cost more than the last.

Xilinx announced the first generation of Spartan FPGAs in 1998. These were 5V devices based on a 0.5µm CMOS process. The company announced 3.3V versions of the original Spartan FPGAs, based on a 0.35µm CMOS process, a few months later. These devices had 238 to 1,862 logic cells and initially sold for $3.95 to $19.95 in 100,000-unit quantities. The first-generation Spartan FPGA design was based on the company’s flagship XC4000 FPGA family, but the Spartan FPGAs had been redesigned to minimize die area and to consume less power, therefore running slower than the higher priced FPGAs. According to Issue 27 of Xcell Journal dated First Quarter 1998, “Xilinx reduced the cost of Spartan devices by not only reducing the die size but by also re-assessing all stages of the manufacturing cycle, including packaging, test, and manufacturing overhead costs.”

Xilinx announced the second-generation Spartan-II FPGAs based on a 250nm CMOS process in 2000. These devices were derived from the company’s XC4000E FPGAs and were the first Spartan FPGAs to split the power supply inputs. The FPGA’s programmable logic fabric ran on 2.5V, and the I/O would run on 1.5V, 2.5V, or 3.3V. Members of the Spartan-II FPGA family were considerably larger than the first-generation Spartan FPGAs, with 432 to 5,292 logic cells.

The third-generation Spartan-3 devices, announced in April 2003, were derived from the company’s Virtex-II FPGAs and were based on a 90nm CMOS process. The Spartan-3 device family would eventually grow to include devices with 1,728 to 74,880 “equivalent logic cells.” Here, Xilinx started to fiddle its published logic cell capacity numbers by converting actual logic cell numbers into equivalents based on 4-input LUTs. According to the Spartan-3 data sheet, the fudge factor was 1.25. The I/O capabilities of this family were greatly expanded and were capable of interfacing to a wide variety of single-ended and differential-pair I/O standards. One of the FPGA industry’s great success stories is the quick replacement of logic-level and interface translators, as demonstrated by the Spartan-3 family’s expanded I/O abilities.

Xilinx really outdid itself with the Spartan-3 device family proliferation, creating the Spartan-3, -3A, -3AN, -3E, and -3ADSP product subfamilies. Each Spartan-3 subfamily emphasized a different capability. Spartan-3A devices maximized I/O pin count. Spartan-3E devices maximized the number of logic elements. The Spartan-3AN devices integrated a separate Flash EEPROM to create a single-chip, SRAM-based FPGA. The Spartan-3ADSP expanded the family’s integrated multiplier blocks with accumulators, turning the multipliers into MACs. All these Spartan-3 subfamilies are now being discontinued.

If you’re keeping score, the discontinued Xilinx PLDs are based on 350nm, 250nm, 180nm, and 90nm CMOS process nodes. Two of those nodes, used for the EPLDs, require additional EEPROM process modules. These are old fab processes that run on old fab lines that are likely sourced by more than one foundry. Given the age of these programmable logic devices, it’s no wonder that they’re being discontinued, with a “last call” on purchases. If you’re thinking of the phrase “planned obsolescence,” then I suggest you consider the following: How easy is it for you to buy a showroom-new vehicle from the 1990s? How about a brand new 1990 stereo receiver? Would you even want a 1999 laptop, when we were running Windows ME? You can’t, you won’t, and you don’t. These PLDs have enjoyed far more longevity than most manufactured products.

Nothing but rust lasts forever.

Acknowledgement: My thanks to Robert Bielby, my former boss when I worked at Xilinx, and his encyclopedic FPGA and CPLD memory.

References

Xcell: The Newsletter for Xilinx Programmable Logic Users, Issue 7, Second Quarter 1992

Xcell: The Newsletter for Xilinx Programmable Logic Users, Issue 19, Fourth Quarter 1995

Xcell: The Newsletter for Xilinx Programmable Logic Users, Issue 20, First Quarter 1996

Xcell: The Newsletter for Xilinx Programmable Logic Users, Issue 27, First Quarter 1998

8 thoughts on “AMD discontinues CoolRunner and XC9500 CPLDs and Spartan-II and -3 FPGAs. Buy ‘em while you can!”

  1. Steve, regarding “remember designing with MMI’s 16L8 PALs in the early 1980s . . . at Cadnetix . . kept a paper cup of programmed PALs on my desk . . . cost about $10 each”

    Those one-time-programmable bipolar PALs used fast titanium tungsten fuses to achieve the speed required to reduce chip count of TTL designs, enabling a single PCB to contain functions like a full possessor, compared to the slow erasable PLDs.

    Thanks for the memories!

  2. Hi jbirkner,

    Glad to hear that this article jogged a few memories. It certainly jogs mine (PALASM, fuse maps, the Structured Design 20/24 I used to burn all of those PALs, and the 16L8 output pins that lacked internal feedback).

    I wrote an entire article about the history of PALs for EEJournal a little more than two years ago:

    https://www.eejournal.com/article/how-the-fpga-came-to-be-part-3/

    It’s based on John Birkner’s oral history at the Computer History Museum. You might have heard of or run into him.

    –Steve

  3. Steve, I am amazed you remember details like the PAL16L8 with output pins lacking internal feedback, PALASM, fuse maps, and the Structured Design 20/24 PAL programmer. Those were the days, exciting times, the paradigm shift to programmable logic technology. And we were there. How far we have come.

    1. John, your PALs were exactly the right product at exactly the right time. Everyone was developing proprietary workstations for CAD and EDA. At that time, most of us were selling hardware bundled with our software, except for Mentor Graphics. PALs went to the heart of CPU design, allowing me to create complex memory-management logic in a compact space at a time when these features were not incorporated into the microprocessors of the day. I remember those experiences like they were yesterday, even though they were 40 years ago. Now, about those missing internal feedback wires…

      1. . . . about those missing internal feedback wires . . .
        referring to figure 1 in your article,
        https://www.eejournal.com/article/how-the-fpga-came-to-be-part-3/
        the PAL16L8 has a symmetric architecture of 8 groups of outputs cells with 8 product term each where the top and bottom cells exchanged feedback for dedicated inputs. The 8-inputs, 8-outputs, 2-inputs/controls, VCC and GND fit perfectly into the space saving 300 mil wide 20-pin Skinny DIP ™, just becoming standard at the time.
        So you could use the dedicated input cells for feedback by connecting them to outputs (pins 1 and 11).
        Those 2 inputs were exchanged for clock and enable on the registered versions, 16R8, 16R6, and 16R4 which were metal mask options on the same basic die as shown in figures at:
        https://ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4124899

  4. I easily understood from a pins-in perspective why there was no feedback on those two outputs from the schematic, John. It’s just that the architectural asymmetry from the pins-out perspective caught me on more than one occasion and PALASM did not complain if I specified an output pin in an equation that had no internal feedback. At least, that’s how I remember it.

  5. Well, those old processes might be dirt cheap, but CPLDs surely are not.

    I’ve been tracking those things for some time now for some retro computer recreations ( they are nifty for using 5V signalling) and they often cost more than a nice entry level FPGA, like Lattice’s ECP5, for example.

    Once you get at 100-ish or more macrocells, their price skyrockets further.

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