We noted recently the slight hesitation taking place in the rush to FinFETs. Some folks are taking another look at FD-SOI as a way of extending planar technology in a more cost-effective manner than what FinFETs promise.
But there’s more to planar than just FD-SOI. Some time back we also surveyed a new approach to planar transistors being pioneered by newcomer SuVolta. At the time, our focus was on how the basic transistor was supposed to work and any proof points that existed then, which were few.
The thing is, when you’re a small startup without your own fab proposing a new transistor, you need to get at least one fab to prove that you’re viable so that other fabs will also take you on. That process tends to be a bit, well, stealthy, so everyone is left to wonder what’s happening.
In fact, filling that vacuum, I had a discussion this summer where I was told that every fab evaluating the SuVolta technology had pulled out of the program, suggesting that things hadn’t been going well. This was roughly a week before I heard from SuVolta directly about their progress. And SuVolta’s update directly countered this rumor (and I asked point blank, and they denied the rumor point blank).
At this time, not only is SuVolta saying they’re coming into their own, but ARM and Fujitsu are saying so as well. Those are not inconsequential names, and they add credibility. Admittedly, I’m one that doesn’t put a lot of stock in the usual “company quotes” in press releases, but these are more than quotes; they’re collaborations.
So let’s start by taking a look at the latest proof points and then move from there into a not-inconsequential question: how can a designer use this technology?
Good to go
The latest data indicating progress has come in two steps. First was the announcement of an implementation of a Cortex M0 core using SuVolta’s deeply-depleted channel (DDC) transistors at the 65-nm process node. Prior to this, all proof points had been from test circuits; this was the first “real” circuit to debut.
The main DDC story is lower power, but that can also be couched as a performance story. The core they implemented was:
- 50% lower power than the non-DDC implementation if speed was kept the same. This was done by reducing what had been a 1.2-V power voltage to 0.9 V.
- 35% faster than the non-DDC version if power was kept the same. Turns out this happens (for this circuit) at VDD=1.1 V.
- 55% faster than the non-DDC version if voltage was kept at the original 1.2 V. This will, of course, burn more power than the original.
These are non-trivial numbers, so on the face of it, this could be pretty attractive.
The other thing they proved out in the same circuit was the ability to lower SRAM power by providing 150 mV more headroom on VDD. In other words, with a lower voltage (hence lower power), the SRAM cell was still able to hold its state.
A few weeks later, Fujitsu, which has been the lead on process integration, announced that it was in volume production on an image processor using the DDC transistors in their 55-nm process. And UMC has hinted that it is working on a 28-nm version of the DDC transistor.
This shows usage from well-established nodes down into more aggressive ones. Of course, how far it can scale will remain a matter of, well, I’ll say conjecture. For us, anyway. Presumably, SuVolta has more concrete info on it, but naysayers will opine against it, so we will be left to see whether this can go to 14 nm or even below 10 nm.
So what do I do with this?
So let’s assume that this thing is real and that it’s here. How do you access the technology? The simple answer is one word: “libraries.” But there’s more to wrap around that.
There are a number of options for working with these transistors. We’ve seen that you can dial up more or less power and more or less performance with them, so how you tune a new circuit will depend on what you want. The possibility of back-biasing adds yet another variable and possible complication.
So SuVolta has given a “marketing” definition to two different approaches. I put marketing in quotes not as a derisive thing (which it might be in other contexts), but rather to clarify that these aren’t really specific programs or products, but rather ways of thinking about – and simplifying – how you can wade into the DDC waters.
The simplest thing you can do is to outright swap old transistors for DDC ones. You can do this only with existing planar transistors – don’t try to mix DDC devices in with FinFETs. SuVolta calls this approach DesignBoost.
The idea is that you take your leakiest transistors and replace them with DDC transistors. This would be rather cumbersome to approach by hand, of course; it can be done simply by referencing the DDC libraries and re-running the tool flow. In synthesizing the new layout, the tools will pull in DDC transistors where needed to meet the power/performance constraints.
Note that you don’t necessarily need to go all the way back to RTL if you don’t want to; you can also replace at the GDS level, although I’d guess some custom scripting will be called for to handle that. And if done on an existing layout, without redoing the layout, the implication must be that the DDC transistor fits into (or at least is no bigger than) the exact footprint of the transistor it’s replacing.
Now, if you look at the ARM data just presented, it says that keeping the same voltage raises performance and power. So you might conclude (as I originally did) that DesignBoost would therefore result in a higher-performance, higher-power circuit (because it’s still being run at the same voltage). And you would be wrong (as I was).
How does that work? Here’s the deal: In the process bring-up, they have designed the basic transistor to match the drive strength of the existing transistor that will be replaced, and no back-bias is required to do that. So from an active circuit standpoint, there should be no difference. Same performance, same power.
But with DDC, that drive current can be achieved with a higher VT. That means less leakage. So the benefit of DesignBoost is to reduce the static leakage power without changing the active behavior. This should allow easy replacement of the older version of the circuit with a DDC version (assuming all other aspects of qualification pan out).
What do you do if want to go beyond what DesignBoost can offer? The other program they have is called PowerShrink. This is where you get in and mess with more of the design to optimize the circuit for use with DDC transistors. Again, it’s all about giving the tools DDC libraries to pull from, but you’re also opening up the range of changes you can make.
With the added possibility (or requirement, in the case of poly gates) of back-biasing, you also need to, for instance, provide well taps. And if you want to bias some transistors differently from others, then you’ll have multiple well-tap domains.
These can be managed first by adding process rules that specify the well tap requirements (like their required spacing). Then, particularly for the case of multiple domains, the floorplan must specify which transistors are in which back-bias domain. But note that these tasks aren’t unique to DDC; they would apply to any circuit or technology employing back biasing.
An important takeaway, then, is that no new EDA technology is needed to do all of this stuff. Existing flows should work just fine.
So at a time when planar is reclaiming some of its street cred, the SuVolta approach provides yet another choice for those who don’t need the performance of a FinFET and who would prefer the lower cost and complexity of 2D transistors for a few more process nodes.
Image: Robert Webb’s Stella software
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What’s your take on SuVolta’s results so far?