industry news
Subscribe Now

SuVolta’s DDC Technology Advancements Further Reduce Power Consumption and Increase Processor Performance

LOS GATOS, Calif., July 23, 2013 – SuVolta, Inc., a developer of scalable semiconductor technologies for low-power, high-performance IC chips, today announced a series of new milestones, advancing its position as a technological innovator. The achievements further validate the company’s approach to solving the power problem at the heart of nearly all electronic systems.

One of the biggest challenges facing chip designers today is reducing power consumption while increasing overall processor performance as consumers expect to run more applications faster on their mobile devices such as smartphones and tablets. In addition, as the Internet of Things continues to become more pervasive, electronics manufacturers need ultra-low power technology for sensors and other key components.

Today’s first announcement is the ARM Cortex-M series processor manufactured with SuVolta’s Deeply Depleted Channel™ (DDC) transistor technology on a 65nm bulk planar CMOS process that shows significant processor speed gains with associated power reduction. Second, SuVolta and United Microelectronics Corporation (UMC) are announcing that the two companies are working jointly on the development of a 28nm low-power process technology that integrates SuVolta’s DDC technology into UMC’s High-K Metal Gate (HKMG) high-performance mobile (HPM) process to target mobile applications.

Also, SuVolta is announcing the appointment of veteran semiconductor executive Dr. Louis Parrillo as the company’s Chief Operating Officer (COO) to help expand the adoption of the DDC technology with more semiconductor manufacturers focused on advanced chip design.

In December 2012, SuVolta announced silicon results demonstrating the performance and power advantages of its DDC transistor technology. SuVolta’s approach based on planar, bulk CMOS enables semiconductor vendors and foundries to continue utilizing their existing design and IP flows without significant retooling or redesign costs thus efficiently extending Moore’s Law.

ARM Says Innovative Ultra-Low Power Technology (based on DDC transistors) Will Be Vital To Ensure ARM Remains at the Forefront of the Internet of Things

When compared to an identical ARM Cortex-M0 processor manufactured in the conventional 65nm process, with a 1.2V supply voltage, the DDC transistor-based ARM implementation operating at 0.9V demonstrates the following benefits:

  • 50 percent lower total power consumption at matched 350MHz operating speed.
  • 35 percent increased operating speed (performance) at matched power.
  • 55 percent increased operating speed when operated at matched supply voltage.

“SuVolta has shown that the DDC technology, when incorporated into an ARM processor, can provide additional power reductions or a significant performance boost. As the Internet of Things continues to expand, innovative ultra-low power technology for sensors and other devices will be vital to ensure that ARM remains at the forefront of this opportunity,” said Noel Hurley, vice president, Strategy and Marketing, Processor Division, ARM.

For details, please read the full press release “SuVolta Announces Speed-Power Benefits of Transistor Technology Validated in ARM Processor.”

UMC’s 28nm High-K/Metal Gate Process Implements SuVolta’s DDC Technology to Target Mobile
Applications

The companies today announced joint technology development of a 28nm low-power process technology. SuVolta and UMC are working together to take advantage of implementing DDC transistor technology to reduce leakage power and improve SRAM low-voltage performance.

The companies also announced that the process technology will enable a highly flexible adoption method:

  • A “DDC PowerShrink™ low-power platform” option for the ultimate power and performance benefit, where all transistors utilize the DDC technology;
  • A “DDC DesignBoost transistor swap” option that works with existing design databases where a subset of transistors are replaced with DDC transistors. Typical applications of this option are replacing the leakier transistors with DDC transistors that could cut leakage, or replacing the SRAM bitcell transistors with DDC transistors to improve performance and lower minimum operating voltage (Vmin)

“In the next weeks and months, we expect to see promising results from joint technology development with SuVolta to further validate the power and performance benefits of the DDC technology in UMC’s 28nm HKMG process,” said T.R. Yew, vice president of Advanced Technology Division at UMC. “By incorporating SuVolta’s advanced technology into our HKMG process, we intend to deliver a 28nm mobile computing process platform to complement our existing Poly-SiON and HKMG technologies.

”For details, please read the full press release “UMC and SuVolta Announce Joint Development of 28nm Low-Power Process Technology.”

New COO Dr. Louis Parrillo Leads DDC Technology Integration Efforts with Partners

As COO, Dr. Parrillo will oversee technology and circuit design programs and resources, working on solutions with leading logic and memory manufacturers, and with fabless semiconductor companies. A renowned semiconductor veteran, Dr. Parrillo has a proven track record in implementing and obtaining results on complex programs both in large companies and start-ups.

“Lou is a valued addition to our executive team to help proliferate our proven silicon-gate transistor technology into broad logic and memory manufacturing,” said Bruce McWilliams, president and CEO of SuVolta. “In addition, Lou’s experience in developing and commercializing technology is a critical asset as our advanced-node metal-gate 28nm and 20nm programs go into production – especially as our manufacturer partner list grows beyond our half-dozen active development partnerships.”

“Whether semiconductor companies are designing applications processors, DRAM, MCUs, image sensors or a variety of other chips, power optimization is key,” said Lou Parrillo, COO at SuVolta. “By advancing technology integration efforts with SuVolta’s partners, we are solving the industry’s greatest challenge – power, affecting the future of semiconductors and mobile computing.”

For details, please read the full press release “SuVolta Appoints Dr. Louis Parrillo as Chief Operating
Office.”

About SuVolta, Inc.

SuVolta, Inc. develops and licenses scalable semiconductor technologies for low-power, highperformance IC chips. Based in Silicon Valley, the team includes world-class engineers and scientists
with a long history of technology development and innovation to advance the semiconductor industry. The
company is backed by leading venture capital firms Kleiner Perkins Caufield & Byers (KPCB), August
Capital, NEA, Bright Capital, Northgate Capital and DAG Ventures. For more information, visit
www.suvolta.com.

To learn more about SuVolta’s technology, visit us at www.suvolta.com/technology/technology-overview/.

For information on licensing SuVolta’s technology, please go www.suvolta.com/sales-inquiry/.

Follow us on Twitter @ http://twitter.com/SuVoltaInc.

Leave a Reply

featured blogs
Apr 23, 2024
Do you think you are spending too much time fine-tuning your SKILL code? As a SKILL coder, you must be aware that producing bug-free and efficient code requires a lot of effort and analysis. But don't worry, there's good news! The Cadence Virtuoso Studio platform ha...
Apr 23, 2024
We explore Aerospace and Government (A&G) chip design and explain how Silicon Lifecycle Management (SLM) ensures semiconductor reliability for A&G applications.The post SLM Solutions for Mission-Critical Aerospace and Government Chip Designs appeared first on Chip ...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

Addressing the Challenges of Low-Latency, High-Performance Wi-Fi
In this episode of Chalk Talk, Amelia Dalton, Andrew Hart from Infineon, and Andy Ross from Laird Connectivity examine the benefits of Wi-Fi 6 and 6E, why IIoT designs are perfectly suited for Wi-Fi 6 and 6E, and how Wi-Fi 6 and 6E will bring Wi-Fi connectivity to a broad range of new applications.
Nov 17, 2023
20,848 views