Synopsys recently announced their HAPS DX (Developer eXpress) product, and the story surrounding that release spoke to many of the things that Synopsys sees as good in their prototyping solution. But a few questions clarified that many of those things have already been available in the existing HAPS offerings. So what’s the key new thing that HAPS DX enables?
Turns out it has to do with the distinction between designing IP and designing an SoC. And this is actually a theme I’m seeing in other contexts as well.
IP started out as mini-designs that were built with the same tools as a full-up chip (or FPGA). Frankly, for a lot of IP companies, the products on the shelf probably wouldn’t have worked for any arbitrary application: they’d need tweaking first. So these products were largely a way to get consulting contracts that would modify the shrunk-wrap IP into something that included all the specifics the client needed.
Even then, folks looked askance at IP, preferring to do it themselves for NIH and control reasons as well as due to the illusion that inside folks were free (or at least already paid for). IP company survival was not a given.
Today it’s assumed that any designer of an SoC will spend a lot of effort (and money) integrating IP; it’s no longer cool to invent a new wheel. But this has changed the nature of design. While full chip design used to be just a bigger version of the process used to design IP, now IP is more about low-level gate design and SoCs are more about assembly (with lower-level design where absolutely necessary).
So now there’s more of a break between where the IP design stops and the SoC design starts, and tools are starting to reflect the challenges of this change of methodology. And that’s the main benefit to the HAPS DX product: it allows for a more seamless transition from IP design to SoC design.
Before, one person might design and verify the IP, and the user then started from scratch, redoing much of the work that the original IP designer did when prototyping. HAPS DX, by contrast, is supposed to help bridge that gap, allowing a more seamless move from IP to SoC with data generated in the IP phase pushed forward for re-use when that IP is integrated.
You can see more of what they’re saying in their announcement.
