editor's blog
Subscribe Now

Smoother IP to SoC Prototyping

Synopsys recently announced their HAPS DX (Developer eXpress) product, and the story surrounding that release spoke to many of the things that Synopsys sees as good in their prototyping solution. But a few questions clarified that many of those things have already been available in the existing HAPS offerings. So what’s the key new thing that HAPS DX enables?

Turns out it has to do with the distinction between designing IP and designing an SoC. And this is actually a theme I’m seeing in other contexts as well.

IP started out as mini-designs that were built with the same tools as a full-up chip (or FPGA). Frankly, for a lot of IP companies, the products on the shelf probably wouldn’t have worked for any arbitrary application: they’d need tweaking first. So these products were largely a way to get consulting contracts that would modify the shrunk-wrap IP into something that included all the specifics the client needed.

Even then, folks looked askance at IP, preferring to do it themselves for NIH and control reasons as well as due to the illusion that inside folks were free (or at least already paid for). IP company survival was not a given.

Today it’s assumed that any designer of an SoC will spend a lot of effort (and money) integrating IP; it’s no longer cool to invent a new wheel. But this has changed the nature of design. While full chip design used to be just a bigger version of the process used to design IP, now IP is more about low-level gate design and SoCs are more about assembly (with lower-level design where absolutely necessary).

So now there’s more of a break between where the IP design stops and the SoC design starts, and tools are starting to reflect the challenges of this change of methodology. And that’s the main benefit to the HAPS DX product: it allows for a more seamless transition from IP design to SoC design.

Before, one person might design and verify the IP, and the user then started from scratch, redoing much of the work that the original IP designer did when prototyping. HAPS DX, by contrast, is supposed to help bridge that gap, allowing a more seamless move from IP to SoC with data generated in the IP phase pushed forward for re-use when that IP is integrated.

You can see more of what they’re saying in their announcement.

Leave a Reply

featured blogs
Apr 11, 2021
https://youtu.be/D29rGqkkf80 Made in "Hawaii" (camera Ziyue Zhang) Monday: Dynamic Duo 2: The Sequel Tuesday: Gall's Law and Big Ball of Mud Wednesday: Benedict Evans on Tech in 2021... [[ Click on the title to access the full blog on the Cadence Community sit...
Apr 8, 2021
We all know the widespread havoc that Covid-19 wreaked in 2020. While the electronics industry in general, and connectors in particular, took an initial hit, the industry rebounded in the second half of 2020 and is rolling into 2021. Travel came to an almost stand-still in 20...
Apr 7, 2021
We explore how EDA tools enable hyper-convergent IC designs, supporting the PPA and yield targets required by advanced 3DICs and SoCs used in AI and HPC. The post Why Hyper-Convergent Chip Designs Call for a New Approach to Circuit Simulation appeared first on From Silicon T...
Apr 5, 2021
Back in November 2019, just a few short months before we all began an enforced… The post Collaboration and innovation thrive on diversity appeared first on Design with Calibre....

featured video

Meeting Cloud Data Bandwidth Requirements with HPC IP

Sponsored by Synopsys

As people continue to work remotely, demands on cloud data centers have never been higher. Chip designers for high-performance computing (HPC) SoCs are looking to new and innovative IP to meet their bandwidth, capacity, and security needs.

Click here for more information

featured paper

Understanding the Foundations of Quiescent Current in Linear Power Systems

Sponsored by Texas Instruments

Minimizing power consumption is an important design consideration, especially in battery-powered systems that utilize linear regulators or low-dropout regulators (LDOs). Read this new whitepaper to learn the fundamentals of IQ in linear-power systems, how to predict behavior in dropout conditions, and maintain minimal disturbance during the load transient response.

Click here to download the whitepaper

featured chalk talk

Time Sensitive Networking for Industrial Automation

Sponsored by Mouser Electronics and Intel

In control applications with strict deterministic requirements, such as those found in automotive and industrial domains, Time Sensitive Networking offers a way to send time-critical traffic over a standard Ethernet infrastructure. This enables the convergence of all traffic classes and multiple applications in one network. In this episode of Chalk Talk, Amelia Dalton chats with Josh Levine of Intel and Patrick Loschmidt of TTTech about standards, specifications, and capabilities of time-sensitive networking (TSN).

Click here for more information about Intel Cyclone® V FPGAs