editor's blog
Subscribe Now

Synopsys’s IP Initiative

IP used to refer to hardware designs that could be purchased off the shelf. Actually, at first they were designs that wouldn’t really work for any real application without a consulting contract to adapt them. But, over time, “shrink wrapped” became more viable. The idea was to save design time.

That idea still holds, but we’ve replaced one problem – design of individual blocks – with another: assembling all of the IP blocks into a complete system. And these IP blocks are more than your grampa’s simple fast Fourier transform; these are typically complete protocols that need to run a software stack.

Once assembled, the system will run the system software that’s being written for the SoC in parallel with the hardware design –software that’s separate from, and likely makes use of, the shrink-wrapped protocol libraries that may accompany the hardware IP.

So the full project development process involves hardware designers getting hardware running – first in prototypes, then in silicon. Meanwhile, software guys are coding away, using both virtual prototypes of the hardware and, eventually, the hardware prototypes that the hardware buys built.

In order to accommodate this more complex flow, Synopsys has announced their IP Initiative. It involves a more holistic view of how IP is integrated into SoCs, and the idea is to make the IP and accompanying elements work out of the box so no time is wasted on things that have already been completed – all of the effort can go into integration.

The image below shows the bigger picture of what they’re trying to accomplish. It includes both existing elements (like the hardware IP) and new elements being released as of the announcement, like the prototyping kits.

Figure.png

The IP prototyping kits are intended for hardware engineers, and they include a working reference design out-of-the-box on a HAPS board. IP licencees will have access to the accompanying IP RTL. Meanwhile, the IP software development kits include tools and virtual platform models of the IP that, again, work out-of-the-box.

The final bit, customized IP subsystems, gets to the challenges of putting all of these pieces together and coaxing them to work. Individual IP blocks work out of the box, but assembling them into an SoC isn’t trivial. Synopsys offers services to help create subsystems out of blocks.

You can read more about their offering in their announcement.

Leave a Reply

featured blogs
Jan 24, 2020
Someone has created a song by taking Pi, assigning each number to a note, and adding harmonies. The result is strangely captivating....
Jan 24, 2020
[From the last episode: We looked at the different ways memory can be organized in different kinds of systems.] Let'€™s look at a scenario: you run a restaurant, but you'€™re short on funds to hire people. So you'€™re your own chief cook and bottle-washer. You do everyt...
Jan 23, 2020
Embedded design trends typically revolve around three main ideas: faster data rates, smaller form factors and cost-effective solutions. Those design trends drive the theme for the 2020 Embedded Tech Trends forum: The Business and Technology Forum for Critical and Intelligent ...
Jan 22, 2020
Master the design and verification of next gen transport: Part One – Overview Master the design and verification of next gen transport: Part Two – High-Level Synthesis Master the design and verification of next gen transport: Part Three – Functional Safety M...

Featured Video

Automotive Trends Driving New SoC Architectures -- Synopsys

Sponsored by Synopsys

Today’s automotive trends are driving new design requirements for automotive SoCs targeting ADAS, gateways, connected cars and infotainment. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet such new requirements and accelerate design time.

Drive Your Next Design to Completion Today with DesignWare IP® for Automotive SoCs