editor's blog
Subscribe Now

Synopsys’s IP Initiative

IP used to refer to hardware designs that could be purchased off the shelf. Actually, at first they were designs that wouldn’t really work for any real application without a consulting contract to adapt them. But, over time, “shrink wrapped” became more viable. The idea was to save design time.

That idea still holds, but we’ve replaced one problem – design of individual blocks – with another: assembling all of the IP blocks into a complete system. And these IP blocks are more than your grampa’s simple fast Fourier transform; these are typically complete protocols that need to run a software stack.

Once assembled, the system will run the system software that’s being written for the SoC in parallel with the hardware design –software that’s separate from, and likely makes use of, the shrink-wrapped protocol libraries that may accompany the hardware IP.

So the full project development process involves hardware designers getting hardware running – first in prototypes, then in silicon. Meanwhile, software guys are coding away, using both virtual prototypes of the hardware and, eventually, the hardware prototypes that the hardware buys built.

In order to accommodate this more complex flow, Synopsys has announced their IP Initiative. It involves a more holistic view of how IP is integrated into SoCs, and the idea is to make the IP and accompanying elements work out of the box so no time is wasted on things that have already been completed – all of the effort can go into integration.

The image below shows the bigger picture of what they’re trying to accomplish. It includes both existing elements (like the hardware IP) and new elements being released as of the announcement, like the prototyping kits.

Figure.png

The IP prototyping kits are intended for hardware engineers, and they include a working reference design out-of-the-box on a HAPS board. IP licencees will have access to the accompanying IP RTL. Meanwhile, the IP software development kits include tools and virtual platform models of the IP that, again, work out-of-the-box.

The final bit, customized IP subsystems, gets to the challenges of putting all of these pieces together and coaxing them to work. Individual IP blocks work out of the box, but assembling them into an SoC isn’t trivial. Synopsys offers services to help create subsystems out of blocks.

You can read more about their offering in their announcement.

Leave a Reply

featured blogs
Dec 5, 2023
Generative AI has become a buzzword in 2023 with the explosive proliferation of ChatGPT and large language models (LLMs). This brought about a debate about which is trained on the largest number of parameters. It also expanded awareness of the broader training of models for s...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Littelfuse Protection IC (eFuse)
If you are working on an industrial, consumer, or telecom design, protection ICs can offer a variety of valuable benefits including reverse current protection, over temperature protection, short circuit protection, and a whole lot more. In this episode of Chalk Talk, Amelia Dalton and Pete Pytlik from Littelfuse explore the key features of protection ICs, how protection ICs compare to conventional discrete component solutions, and how you can take advantage of Littelfuse protection ICs in your next design.
May 8, 2023
27,039 views