editor's blog
Subscribe Now

Sophisticated Variation Modeling

As a newly-developed process is prepared for delivery into the production world, one of the last things that has to happen to effect a transition is the development of compact models for use in design simulation. And, of course, these days, such a model must account for process variations, which means covering the wide range of corners that a process can have to capture the statistics.

We’ve seen some of this before with Solido, but according to newcomer GSS, whom my colleague Dick Selwood explored at some length back when GSS was getting started, most other tools model processes as Gaussian, and the world isn’t actually Gaussian. Also, the existing tools help with simulation, but they don’t create a model.

Well, GSS has now released their tool. It works as a “wrapper” to a simulator, as these tools are wont to do. So it doesn’t do the actual simulation; you pick whatever simulator you want to work with, along with the circuit and model strategy, and the GSS tool creates the corners to be run – on the order of a couple thousand runs. Because of the independence of the runs, this scales perfectly with additional processors; you specify the number of processors and it handles the load management.

It then builds a model with statistical features that no other models have; the model itself has time-dependent capabilities for characteristics that evolve over time. In this manner, they say that it bridges TCAD and production EDA in a way that no other tool does.

They announced their tool in a somewhat indirect fashion, focusing on the possibility of unforeseen SRAM yield issues at the 20-nm node. You can see more about the details of that discussion in their release.

Leave a Reply

featured blogs
Apr 19, 2024
In today's rapidly evolving digital landscape, staying at the cutting edge is crucial to success. For MaxLinear, bridging the gap between firmware and hardware development has been pivotal. All of the company's products solve critical communication and high-frequency analysis...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

Optimize Performance: RF Solutions from PCB to Antenna
Sponsored by Mouser Electronics and Amphenol
RF is a ubiquitous design element found in a large variety of electronic designs today. In this episode of Chalk Talk, Amelia Dalton and Rahul Rajan from Amphenol RF discuss how you can optimize your RF performance through each step of the signal chain. They examine how you can utilize Amphenol’s RF wide range of connectors including solutions for PCBs, board to board RF connectivity, board to panel and more!
May 25, 2023
37,157 views