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CAST Offers the First 12-bit JPEG Extended Sequential, DICOM-Compatible IP Core

WOODCLIFF LAKE, N.J., April 13 — Semiconductor intellectual property (IP) provider CAST, Inc. now offers the only encoder core that supports both the Baseline (8-bit) and Extended Sequential (12-bit) modes of the JPEG image compression standard.

This plus a fast, compact design make the new JPEG-E-X IP core one of the best available lossy compression encoders for medical imaging, reconnaissance, and other applications where exceptional image detail is required.

Read More → "CAST Offers the First 12-bit JPEG Extended Sequential, DICOM-Compatible IP Core"

Synopsys’ DesignWare SuperSpeed USB 3.0 IP receives USB-IF certification

MOUNTAIN VIEW, Calif. – March 31, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that its DesignWare(R) SuperSpeed USB (USB 3.0) Solution including Controller and PHY IP  successfully passed the USB Implementers Forum (USB-IF) SuperSpeed USB certification. To achieve certification, the IP must pass protocol, electrical, and interoperability tests for SuperSpeed USB (USB 3.0, 5 Gbps) and Hi-Speed USB (USB 2.0, 480 Mbps). Synopsys created a fully integrated USB 3.0 IP solution, optimising all speed modes into a single USB 3.0 solution. This unique implementation enables designers to reduce area, pin count and power compared … Read More → "Synopsys’ DesignWare SuperSpeed USB 3.0 IP receives USB-IF certification"

SiliconBlue selects Synopsys as FPGA synthesis partner for its iCE65 mobileFPGA family

MOUNTAIN VIEW, Calif., and SANTA CLARA, Calif., March 31, 2010 — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and SiliconBlue, a leader in ultra-low power, single-chip SRAM FPGAs, today announced that SiliconBlue has chosen Synopsys Synplify Pro® FPGA synthesis software as the synthesis tool of choice for its iCE65™ family of mobileFPGA™ devices.  SiliconBlue will distribute with its iCEcube™ software a version of the Synplify Pro software optimised for iCE65 devices. This version of the Synplify Pro software will have a thorough understanding … Read More → "SiliconBlue selects Synopsys as FPGA synthesis partner for its iCE65 mobileFPGA family"

D-Tools Enhances Manufacturer Vantage Point (MVP) Program with Legacy Partner, AudioControl

CONCORD, CA. MARCH 30, 2010 – D-Tools, Inc., the worldwide leader in system integration software, today announced that AudioControl has renewed their D-Tools Manufacturer Vantage Point (MVP) program Partnership. AudioControl is a U.S. based designer and manufacturer of audio analyzers, signal processors and distributed audio products. AudioControl has recently had their whole product line updated, better enabling D-Tools System Integrator™ users to specify AudioControl high-end products to their end customers. 

During D-Tools inception year of 1998, AudioControl became known as D-Tools first partner and now over ten years later, … Read More → "D-Tools Enhances Manufacturer Vantage Point (MVP) Program with Legacy Partner, AudioControl"

Cypress Introduces PSoC 3® and PSoC 5 Device Selection Tool To Help Designers Easily Customize the Perfect PSoC Solution

SAN JOSE, Calif., March 30, 2010 – Cypress Semiconductor Corp. (Nasdaq: CY) today introduced a new online product selection tool for its powerful new PSoC® 3 and PSoC 5 architectures. The Electronic Product Selector Guide, now available at Read More → "Cypress Introduces PSoC 3® and PSoC 5 Device Selection Tool To Help Designers Easily Customize the Perfect PSoC Solution"

Synopsys Galaxy Implementation Platform enables first-pass silicon success on Infineon’s 40-nanometer X-GOLD 626 wireless product

MOUNTAIN VIEW, Calif., March 30, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that the Galaxy™ Implementation Platform has helped Infineon Technologies AG (NYSE: IFX) achieve first-pass silicon success of the 40-nanometer (nm) baseband processor for its X-GOLD™ 626 3G wireless analogue and digital system-in-package (SIP). Infineon utilised the Galaxy platform’s powerful implementation flow to optimise the chip’s multiple functional modes with multi-corner/multi-mode (MCMM) technology, taking advantage of the links between Synopsys’ Design Compiler® RTL synthesis solution and IC Compiler placement … Read More → "Synopsys Galaxy Implementation Platform enables first-pass silicon success on Infineon’s 40-nanometer X-GOLD 626 wireless product"

EnSilica launches major new version of its eSi-RISC Development Suite

Wokingham and Cambridge, UK – March 29, 2010.  EnSilica, a leading independent provider of front-end IC design services, has launched a major new version of its eSi-RISC Development Suite.  The eSi-RISC Development Suite v2.1 provides a comprehensive platform for easily evaluating EnSilica’s family of eSi-RISC highly configurable and low-power soft processor cores, along with a complete development environment for the creation, implementation and test of eSi-RISC processor embedded application designs.

Read More → "EnSilica launches major new version of its eSi-RISC Development Suite"

Design Compiler 2010 doubles productivity of synthesis and place and route

MOUNTAIN VIEW, Calif., 29th March – Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today introduced Design Compiler® 2010, the latest RTL synthesis innovation within the Galaxy™ Implementation platform, which delivers a twofold speedup in the synthesis and physical implementation flow. To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimise iterations to speed up physical implementation. To address these challenges, topographical technology in Design Compiler 2010 is being extended to produce “physical guidance” to Synopsys’ flagship … Read More → "Design Compiler 2010 doubles productivity of synthesis and place and route"

Tanner EDA and Dongbu HiTek Semiconductor Jointly Develop Foundry-certified Process Design Kits (PDKs) for Critical Process Nodes

MONROVIA, California and SEOUL, Korea – March 24, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and Dongbu HiTek, a world-class wafer fabricator, are jointly developing foundry-certified process development kits (PDKs) that will be integrated seamlessly into Tanner’s cohesive, integrated tool flow. Designers using Tanner software solutions will have certified libraries to draw on as they create ICs at critical process nodes for production at Dongbu foundries, reducing design risk and providing faster time to market and … Read More → "Tanner EDA and Dongbu HiTek Semiconductor Jointly Develop Foundry-certified Process Design Kits (PDKs) for Critical Process Nodes"

ASTER announces the first DfT software to combine Electrical and Mechanical analysis

Cesson-Sévigné,  France, March 2010 — During APEX 2010 at the New Mandalay Bay Resort & Convention Center in Las Vegas, ASTER Technologies, the leading supplier in Board-Level Testability and Test Coverage analysis tools, will introduce the first Design for Test (DfT) software to combine electrical and mechanical analysis.

It has been developed to address a new vision of the DfT market that has to solve the many challenges that developers face today, such as: shrinking release cycles, budget compression and improvement in product quality.

TestWay, the world-wide reference … Read More → "ASTER announces the first DfT software to combine Electrical and Mechanical analysis"

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