Synopsys, Inc. (Nasdaq:SNPS) today announced the industry’s first demonstration of MIPI® D-PHY IP on TSMC’s 16-nanometer (nm) FinFET Plus (16FF+) process operating at 2.5 Gbps per lane. The demonstration shows the DesignWare® D-PHY receiver (Rx) lane connected to Keysight Technologies’ test equipment, which provided burst-mode stimulus for stressed eye testing and the transmitter (Tx) lane connected to the Keysight oscilloscope displaying the transmitter’s performance. The DesignWare MIPI D-PHY operating at very high speeds on the 16FF+ process, enables designers to meet their power and performance requirements while ensuring interoperability with the latest image sensors and displays. Synopsys’ silicon-proven D-PHY IP is compliant with the MIPI D-PHY v1.2 specification and delivers 50 percent lower power and smaller area compared to other competitive solutions.
“Keysight and Synopsys collaborated to validate the performance and compliance of the DesignWare MIPI D-PHY IP, helping designers lower the risk of incorporating the IP into their SoCs,” said Jurgen Beck, vice president and general manager at Keysight Technologies. “This industry first demonstration underscores both companies’ commitment to providing designers with high-quality IP and testing solutions that enable them to meet their design requirements and achieve silicon success.”
“As Chair of the MIPI D-PHY Sub-Group, Synopsys is leading the development of the specification and closely collaborating with the Working Group members to drive adoption,” said Joel Huloux, chairman of the board of MIPI Alliance. “Demonstrating its MIPI D-PHY v1.2 IP running at 2.5 Gbps gives designers confidence in their ability to integrate the DesignWare MIPI D-PHY in their SoC designs today.”
“Synopsys’ demonstration gives designers assurance that they can incorporate DesignWare MIPI D-PHY IP into their SoC with confidence, while meeting their power and performance goals on the advanced 16FF+ process,” saidJohn Koeter, vice president of marketing for IP and prototyping at Synopsys. “Synopsys’ MIPI IP solutions have been used in hundreds of designs. This successful track record combined with the demonstration enables designers to incorporate a high-quality D-PHY solution into their SoCs with minimal risk.”
Availability
Synopsys’ DesignWare MIPI D-PHY, CSI-2 and DSI IP are available now in a variety of advanced processes. The verification IP for these interfaces is also available now. For more information visit the MIPI Alliance Open and Demo Day Taipei 2015.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 16th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also growing its leadership in software quality and security solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
