fish fry
Subscribe Now

The Beat Goes On

The Cadence of IoT and the Sound of a Single Atom

The music is loud, the rhythm – infectious, but it’s the backbeat that has us tapping our toes and coming back for more. We’re all jamming to the same IoT tune, but what keeps the cadence in 4/4 time? My guest this week is Phil Callahan from Silicon Labs and we discuss this dance called IoT, from the internet infrastructure laying down its chord progression to the super cool demo solos Silicon Labs will be showing at this year’s X-fest. Also this week, we check out another musical melody that has finally revealed…the sound of a single atom. 

 

 

Download this episode (right click and save)

Links for September 26, 2014

Propagating phonons coupled to an artificial atom (Research Article)

More information about Silicon Labs IoT solutions

More information about Silicon Labs solutions for internet infrastructure

New Episode of Chalk Talk: Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

More information about X-fest

Register for X-fest


Leave a Reply

featured blogs
Aug 16, 2018
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding i...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...