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The Shifting Startup Scene

The seed of a technology startup has always been the same – expertise plus idea. Someone with a particular skill or expertise (and some entrepreneurial spirit) comes up with a novel idea and decides to “make a go of it” – creating a new company. The first part is easy, as most engineers are working completely in their comfort and competence zone. They get a couple of laptops, scopes, … Read More → "The Shifting Startup Scene"

Walking the (Heterogeneous Multiprocessing) Talk

For years now, marketing folks at companies who make things like GPUs and FPGAs have been painting a beautiful picture of a gleaming future – a future where dogs and cats get along, unicorns frolic on the lawn, and accelerated computing brings orders of magnitude improvements in computational throughput and, particularly, performance-per-watt. It’s a grand story, and the only thing that’s kept it from becoming reality is the … Read More → "Walking the (Heterogeneous Multiprocessing) Talk"

Cars, Connection and Silicon

How do you sum up embedded world, this year spread over three days, with nearly 40,000 people and over 1,000 exhibitors, all around a theme of Securely Connecting the Embedded World?  Well you can’t – not sensibly. Instead I am going to look at a thread that recurred in the dozens of conversations that I had in those three days and that is currently a hot topic. Obviously, the IoT was … Read More → "Cars, Connection and Silicon"

DynamIQ Tension

“As a rule, a beautiful woman is a terrible disappointment.” – Carl Jung

You want the short version? Some future ARM processors will support 8-CPU clusters.

You want the longer version? “This redefines multicore. Designed from the ground up. Massive system performance uplift. 10x faster. 50x faster. Architecture for total computing. An industry inflection point. Accelerates AI adoption. Safer autonomous systems. For all markets … Read More → "DynamIQ Tension"

Data Center Duel Deux

It’s clear that programmable logic and FPGA technology will capture an increasing share of the value in conventional and cloud data-center deployments. While FPGAs have always been used in connectivity and storage, there is an ever-building push to have high-end FPGAs take over a crucial role in computation as well. FPGAs pack a potent combination of massive computational throughput, low latency, and power efficiency that is … Read More → "Data Center Duel Deux"

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featured blogs
May 26, 2017
From 15-17 May CDNLive EMEA opened again its doors for around 700 attendees from all over Europe, who want to know more about the new products from Cadence. For the 10 th time Cadence Academic Network has organized an Academic Track , which definitely was a reason to celebrat...
May 26, 2017
In this week’s fish fry, we get down into the nitty gritty details of real time operating systems for wearable devices. Kim Rowe (founder and CEO of RoweBots) joins Fish Fry to discuss the future of machine-to-machine communication, the evolution of sensor tech...
May 26, 2017
Between overdue books, too many “Quiet Please” signs to count, and trying to navigate the Dewey Decimal System, going to the library is never much fun.  The same feeling is often true when searching for technical documentation before, during, or after the desig...
chalk talks
Simulating Systems with PSpiceSimple simulation just doesn't cut it with today's complex board designs. To manage the tradeoff between accuracy and performance, you need a variety of models with multiple levels of abstraction. In this episode of Chalk Talk, Amelia Dalton chats with Parag Choudhary of Cadence Design Systems about simulating with PSpice.
Synplify FPGA SynthesisToday’s FPGAs demand a lot from your design tool environment, particularly when it comes to synthesis. With larger designs, more third-party IP, globally-distributed design teams, and increasing performance and power challenges, the demands on synthesis technology are greater than ever. In this episode of Chalk Talk, Amelia Dalton chats with Joe Mallett of Synopsys about … Read More → "Synplify FPGA Synthesis"
Vivado Design Suite HLx EditionsHigh-level design methods can dramatically increase your productivity. Now that technologies like high-level synthesis (HLS) have gone mainstream, we can make some serious improvements to our FPGA design process. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven of Xilinx about how the new HLx editions of Vivado Design suite are taking high-level design mainstream.
Stratus™ High-Level SynthesisHigh-Level Synthesis (HLS) has been gaining traction in the mainstream for the past couple of years. But, HLS is good for a lot more than just increasing development productivity. In this episode of Chalk Talk, Amelia Dalton chats with David Pursley of Cadence Designs Systems about the new Stratus High-Level Synthesis technology, and how it … Read More → "Stratus™ High-Level Synthesis"
Announcing Indago Debug PlatformDebugging your design should be a lot more sophisticated than a bunch of “printf” statements. But that is exactly what many development teams end up using. In this episode of Chalk Talk, Amelia Dalton chats with Adam Sherer of Cadence Design Systems about the new Indago embedded debug system. It will change the way you … Read More → "Announcing Indago Debug Platform"
Top 10 Reasons Real Signal Integrity Engineers Demand Power-Aware SI TechnologySignal Integrity analysis that doesn’t consider power effects can set you up for some dangerous problems. Ground bounce and other effects can cause problems that normal SI tools won’t detect. In this episode of Chalk Talk, Amelia Dalton discusses power-aware signal integrity analysis with Brad Griffin of Cadence Design Systems. You’ll want to watch to … Read More → "Top 10 Reasons Real Signal Integrity Engineers Demand Power-Aware SI Technology"