industry news
Subscribe Now

SuperTest – helping to lead the RISC-V revolution at SiFive

California-based SiFive is a semiconductor IP company founded in 2015 by the inventors of the open RISC-V instruction set architecture. Its semiconductor IP ranges from high-performance application processors and vector processors to low-power embedded 64- and 32-bit microcontrollers. SiFive was the first company to design a quad-core RISC-V CPU capable of running fully featured Linux distributions. SiFive generates revenue by licensing its RISC-V processor core IP. The company’s HiFive development boards are supported by an IDE that includes a GCC and LLVM compiler toolchain.

SiFive is currently building a new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery, and SoC development. These new developments include state-of-the-art compiler algorithms, novel build system integration, and new Verilog RTL generation techniques. SiFive needed a powerful compiler test and verification tool, not only to verify the functionality of its existing compiler offering, but also to help develop its new IDE infrastructure. The tool SiFive chose was SuperTest from Solid Sands.

“Several of the new developers we hired over the last few years already had experience using SuperTest, so we started with a very good understanding of what it was capable of,” said Sam Grove, Director, Product Management, SiFive. “It has already helped us to build and verify a high-quality toolchain that our customers can use straight out of the box.”

Sam and his team currently use SuperTest for verification and testing of the GCC and LLVM compilers and libraries it supplies with its IDE, as well as for regression and release testing. Over the two years the company has been using it, SuperTest has helped to identify several previously unknown code generation errors in both compiler systems.

“SuperTest takes virtually no effort to set up and use,” said Richard Fuhler, Director, Compiler Development, SiFive.

Leading the RISC-V revolution

With its origins in the original research that led to the RISC-V architecture, SiFive is the leading provider of RISC-V IP and one of the leading contributors at RISC-V International, the non-profit organization that supports the free and open RISC-V instruction set architecture and extensions. The attractions of RISC-V are two-fold. Firstly, the ISA is licence-free, removing the cost barrier for adoption by commercial, research or academic users. Secondly, the architecture is modular, extensible and customizable, allowing the addition of unique application-specific instructions and hardware acceleration features at the architecture level, while also leveraging the benefits of industry-wide development of ratified standards for extensions.

For example, SiFive has recently introduced its SiFive Intelligence X280, which extends RISC-V with SiFive Intelligence Extensions that integrate dedicated AI acceleration technology and extended data type support into the RISC-V instruction set architecture. With comprehensive support for TensorFlow Lite, the result is a programmable, scalable, and configurable platform to meet modern AI/ML processing requirements from the edge to the cloud, providing out-of-the-box compatibility with a wide range of popular machine learning models.

Because adding application-specific instructions has implications for the compiler and potentially also the libraries, similar enhanced RISC-V architecture developers may want to take advantage of SuperTest’s comprehensive verification capabilities, notably its CGTrainer code generator trainer, which provides a systematic way of testing a modified compiler’s back end. In such situations, SuperTest also provides a way of checking that the basic functionality of the compiler − its correct implementation of the C or C++ language specification − is not broken by the addition of these new instructions.

About Solid Sands

Founded in 2014, Solid Sands is the one-stop shop for C and C++ compiler and library testing, validation and safety services. Solid Sands offers extensive test and validation suites with a unique level of compiler and library test coverage, enabling customers to achieve the software tool quality level demanded by ISO standards. The company’s name combines sand – the world’s most abundant source of silicon – with the solidity and security expected of sector-leading testing and validation technologies. More information on the company’s products and services is available at www.solidsands.nl. You can follow Solid Sands on LinkedIn, Twitter and YouTube.

Leave a Reply

featured blogs
May 2, 2024
I'm envisioning what one of these pieces would look like on the wall of my office. It would look awesome!...
Apr 30, 2024
Analog IC design engineers need breakthrough technologies & chip design tools to solve modern challenges; learn more from our analog design panel at SNUG 2024.The post Why Analog Design Challenges Need Breakthrough Technologies appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Achieve Greater Design Flexibility and Reduce Costs with Chiplets

Sponsored by Keysight

Chiplets are a new way to build a system-on-chips (SoCs) to improve yields and reduce costs. It partitions the chip into discrete elements and connects them with a standardized interface, enabling designers to meet performance, efficiency, power, size, and cost challenges in the 5 / 6G, artificial intelligence (AI), and virtual reality (VR) era. This white paper will discuss the shift to chiplet adoption and Keysight EDA's implementation of the communication standard (UCIe) into the Keysight Advanced Design System (ADS).

Dive into the technical details – download now.

featured chalk talk

GaN Solutions Featuring EcoGaN™ and Nano Pulse Control
In this episode of Chalk Talk, Amelia Dalton and Kengo Ohmori from ROHM Semiconductor examine the details and benefits of ROHM Semiconductor’s new lineup of EcoGaN™ Power Stage ICs that can reduce the component count by 99% and the power loss of your next design by 55%. They also investigate ROHM’s Ultra-High-Speed Control IC Technology called Nano Pulse Control that maximizes the performance of GaN devices.
Oct 9, 2023
26,847 views