San Jose, CA – Jun 30, 2020 – Silexica (silexica.com) has announced the release of SLX FPGA 2020.2 which includes several usability improvements for new and advanced HLS users. The new Vivado/Vitis HLS project importer quickly and easily enables engineers to import an existing Xilinx HLS project to evaluate and get started with SLX FPGA. Further optimizations in the SLX FPGA analysis engine, combining both static and dynamic analysis, result in 7x faster, on average, analysis time during parallelism detection. Faster analysis time allows for more design space exploration in a shorter amount of time.
“SLX FPGA is an indispensable tool when using high-level synthesis,” said Bertrand Rousseau, CTO of ECSPEC. “The analysis tools helped us focus on the bottlenecks in our code, and the automated design space exploration allowed us to evaluate many more possibilities than we ever could manually.”
An overview of how SLX FPGA addresses the needs of new and advanced HLS users is demonstrated in Silexica’s latest blog article High-Level Synthesis: How to solve common challenges for new and experienced users. It shows how SLX FPGA empowers a new HLS user to be successful in their first design by providing an understanding of the multiple options to fix synthesizability issues and exploit parallelism successfully.
Silexica’s recently published white paper, High-level Synthesis: Can it outperform hand-coded HDL?, gives an example of how advanced users benefit from the latest version of SLX FPGA. It highlights how SLX FPGA, on a real-world case study, can both automatically insert pragmas for better performance and also provide deep code insights to guide code refactoring. The final HLS implementation optimized with SLX FPGA is 64% faster compared to the handwritten HDL implementation with a fraction of the time to complete the design.
SLX FPGA Supports New and Advanced HLS Users to Overcome HLS Challenges
Adopting an HLS methodology presents challenges that must be considered and overcome during the design process. SLX FPGA tackles the problems associated with the HLS design flow, including non-synthesizable C/C++ code, non-hardware aware C/C++ code, application parallelism detection, and determination of which pragmas to insert and the pragma attributes to help engineers prepare and optimize their C/C++ application code for HLS.
New Usability Enhancements Include:
- New Vivado/Vitis project importer to get started easier with SLX FPGA
- Faster analysis time to enable more design exploration
- Alignment of compiler versions between Silexica and Xilinx for smoother compiles
- Function Mapping Editor has been extended with additional interface types
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About Silexica
Silexica provides software development tools allowing technology companies to take innovative IP and intelligent products from concept to deployment. Enabled by metrics-driven software analysis and execution behavior insights, the SLX programming tools disrupt the journey from software to application-specific hardware.
Founded in 2014, Silexica is headquartered in Germany with offices in the US, Japan, and Pakistan. It serves innovative companies in the automotive, robotics, wireless communications, aerospace, and financial industries and has received $28M in funding from international investors.
