SAN MATEO, Calif. — April 10, 2019 — SiFive, the leading provider of commercial RISC-V processor IP, today announced the launch of the S2 Core IP Series at the Linley Spring Processor Conference in Santa Clara. The S2 Core IP Series is a 64-bit addition to SiFive’s 2 Series Core IP and brings advanced features to SiFive’s smallest microcontrollers. The S2 Series further adds to SiFive’s extensive, vastly customizable, optimized, silicon-proven, embedded core IP portfolio, which comprises the 2, 3, 5, and 7 Core IP Series in E (32-bit) and S (64-bit) variants.
Edge SoCs face the diverse requirements of real-time latency, deterministic capability and stringent power constraints. The S2 enables SoCs to have an always-on low power CPU that can be combined with high-performance CPUs that switch on only when applications demand performance, such as in voice-activated smart devices. The 2 Series can be configured to be as small as just 13,500 gates (in RV32E form). The S2 is just half the size of a similarly configured S5 core. Security is enhanced by separation between secure and non-secure domains. This degree of flexibility is what is needed to meet the constraints in terms of power, area and real-time demands as well as the requirements in terms of performance of modern edge workloads and applications. The S2 Series will be available as a customizable Core IP Series as well as in the form of standard cores via SiFive’s Core Designer.
“SiFive’s 64-bit S Cores bring their hallmark efficiency, configurability and silicon-proven Core IP expertise to 64-bit embedded architectures,” said Ted Speers, head of product architecture and planning at Microchip Technology’s Microsemi subsidiary and RISC-V Foundation board member. “The S Cores will enable innovation for the next generation of embedded compute.”
The ever-growing number of connected devices with artificial intelligence, machine learning, IoT, and real-time workloads have generated a massive demand for greatly enhanced embedded intelligence in compute at the edge. Legacy architectures have long ignored the need for small, efficient, 64-bit, real-time embedded processors. SiFive has secured more than 25 design wins for the 2 Series Core IP alone since its launch at DAC in June 2018 and is now launching the S2 Series for power- and area-constrained, high performance 64-bit embedded applications. The S2 has no direct competitive equivalent in the market in terms of offering 64-bit capabilities or advanced features within the footprint of a SiFive 2 Series Core IP. The 64-bit capability of the S2 allows for far easier integration than 32-bit physical addressing and provides the benefit of fast and efficient access to slow or far-away memories via flexible memory maps and micro instruction caches. SiFive is the sole RISC-V Core IP provider to offer 64-bit fully coherent heterogenous compute all the way up to nine cores per cluster where high-throughput processing is needed. Existing and new features are shared across E and S variants of the 2 Series, which include enhanced debug and trace.
“To achieve SiFive’s mission to democratize silicon and compute, we must rapidly enable embedded intelligence where data touches the real world,” said Yunsup Lee, CTO and co-founder, SiFive. “SiFive recognized a deep need for a full 64-bit embedded solution. We leveraged our unique methodology to rapidly innovate and architect 64-bit, fully heterogenous and coherent, real-time core capability. Our S2 Core IP Series is silicon proven and brings efficiency, performance, and security to enable greater innovation at the edge.”
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit www.sifive.com.