Imperas Software Ltd, the leader in RISC-V simulation solutions, today announced the release of the first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores. The initial release is for RV32IMC, RV64 and other ratified extensions are under development and will also be released as part of the popular Read More → "Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library"

Elk Grove, Calif., August 2, 2022 — Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of a Proposed Working Group (PWG) to focus on defining a standard Clock Domain Crossing (CDC) collateral specification to ease SOC integration.

“At Accellera, we create and deliver standards that enhance the design and verification productivity of electronic products,” stated Lu Dai, Chair of Accellera. “Our members elevate the need for standards that will be beneficial to their projects. Currently, collateral … Read More → "Accellera Announces Proposed Working Group to Explore Clock Domain Crossing Standard"