industry news
Subscribe Now

Accellera Announces Proposed Working Group to Explore Clock Domain Crossing Standard

Group to Gather Industry Input on Requirements and Need for Standards Development Project

Elk Grove, Calif., August 2, 2022 — Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today the formation of a Proposed Working Group (PWG) to focus on defining a standard Clock Domain Crossing (CDC) collateral specification to ease SOC integration.

“At Accellera, we create and deliver standards that enhance the design and verification productivity of electronic products,” stated Lu Dai, Chair of Accellera. “Our members elevate the need for standards that will be beneficial to their projects. Currently, collateral generated from different CDC verification tools are not interoperable with each other. Our new Clock Domain Crossing Standardization PWG aims to address this issue. We look forward to input from the community and encourage all interested companies to join the PWG and provide guidance on the need for a standard in this area.”

“Typically, the CDC verification tools that the IP and SoC teams use rely on different formats to capture CDC intent,” stated Martin Barnasconi, Accellera Technical Committee Chair. “Based on the level of interest and commitment from the community, the PWG will determine if a standard is needed to enable the interoperability of CDC collateral generated by different CDC verification tools to ease integration. If your company is interested in providing input, please join us for the initial kick-off meeting in September.”

The first Proposed Working Group meeting will be held Tuesday, September 13th from 9am – 4pm PT at Intel SC12, 3600 Juliette Lane, Santa Clara, SC12-538. Register for the meeting here. For more information about the PWG, visit here.

Participants in the PWG need not be from Accellera member companies. Companies that have already shown interest in participating in the kick-off meeting include Arm, Cadence, Intel, Qualcomm, NVIDIA, NXP, STMicroelectronics and Siemens.

Background on Clock Domain Crossing Standardization Proposed Working Group
SoC teams cannot reuse IP-level CDC collateral in the SoC environment if both teams use different CDC verification tools. This scenario is causing a CDC verification problem when the SoC teams source IP from IP providers that use a different tool for their own CDC verification. To perform holistic SoC-level verification, additional resources are needed to reconverge the IP with the verification tool used by the SoC team. Redoing IP-level CDC verification is time consuming and labor intensive. Standardization on CDC collateral will bring significant benefit to not only product companies, but also IP design houses, EDA tool companies, and the entire ecosystem. The PWG will collect requirements, identify technical feasibility, identify industry interest and acceptance, and provide a recommendation to start or not start a working group. 

About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for-profit organization dedicated to create, support, promote and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter and LinkedIn or to comment, please use #accellera. Accellera Global Sponsors are: Cadence, Siemens EDA, and Synopsys.

Leave a Reply

featured blogs
Apr 24, 2026
A thought experiment in curiosity, confusion, and cosmic consequences....

featured paper

Quickly and accurately identify inter-domain leakage issues in IC designs

Sponsored by Siemens Digital Industries Software

Power domain leakage is a major IC reliability issue, often missed by traditional tools. This white paper describes challenges of identifying leakage, types of false results, and presents Siemens EDA’s Insight Analyzer. The tool proactively finds true leakage paths, filters out false positives, and helps circuit designers quickly fix risks—enabling more robust, reliable chip designs. With detailed, context-aware analysis, designers save time and improve silicon quality.

Click to read more

featured chalk talk

Connecting the World Through Space
Sponsored by Mouser Electronics and Qorvo
In this episode of Chalk Talk, Ryan Jennings from Qorvo and Amelia Dalton explore the critical components and design challenges inherent in LEO satellite infrastructure and how Qorvo’s solutions are enabling the next generation of space-based connectivity. 
Mar 30, 2026
26,184 views