CAMPBELL, Calif. – June 1, 2011 – Sigrity, Inc., the market leader in signal and power integrity solutions, today announced the SystemSI™ family of signal integrity analysis solutions – the industry’s first comprehensive environment for end-to-end simulations of high-speed signal interfaces. Unlike previous approaches that analyze timing margin phenomena in an isolated, piecemeal manner to predict overall margins, Sigrity’s SystemSI family brings everything together within a single environment to streamline the development of high-speed products. It includes a block-based editor, support for standard modeling formats, automated model connections and highly accurate simulation, resulting in the … Read More → "Sigrity Takes High-Speed Chip-to-Chip Analysis to the Next Level with SystemSI"

SAN JOSE, Calif.  June 2, 2011 –   Solido Design Automation Inc., the leading provider of variation analysis and design software for custom integrated circuits, today announced that TSMC has expanded Solido Variation Designer deployment in its Analog/Mixed-Signal (AMS) Reference Flow 2.0, a critical component of TSMC’s 28nm design infrastructure.  Solido Variation Designer products will be included in the following five TSMC AMS sub flows:

• Advanced PVT sub flow
• Advanced Monte Carlo sub flow
• Layout-Dependent Effects (LDE) Constraint Creation sub flow
• Parasitic Constraint Creation … Read More → "Solido for Variation Analysis and Design in TSMC Analog/Mixed-Signal Reference Flow 2.0"

San jose, calif., June 1, 2011 —Pulsic, the premier provider of physical design tools for custom design automation, will introduce the Pulsic Planning Solution™ at DAC 2011 in San Diego. A completely integrated full-chip solution built ‘from the ground up’ for custom, analog and mixed-signal (AMS) integrated circuits (ICs), the Pulsic Planning Solution automates planning and top-level routing functionality. The Pulsic … Read More → "Pulsic to Introduce Integrated, Full-chip Planning and Top-level Routing Solution for Custom IC Design at DAC 2011"

SAN JOSE, CALIF. –– June 1, 2011 –– Forte Design Systems™ today began shipping the latest version of its Cynthesizer™ SystemC high-level synthesis (HLS) software, offering improved performance and quality of results (QoR).

Over the last six months, the Forte R&D team added new features and improved existing features to Cynthesizer, used in more than 300 production application specific integrated circuit (ASIC) and system-on-Chip (SoC) silicon tapeouts since 2002.  Upgrades across the entire tool make it … Read More → "Forte Design Systems Ships Latest Version of Cynthesizer High-Level Synthesis"

FREMONT, Calif., June 1, 2011 – ClioSoft, Inc., developer of the premier hardware configuration management (HCM) solutions for the electronics design industry, will demonstrate its SOS Design Collaboration Platform and introduce a new hierarchical Visual Design Diff (VDD) at DAC 2011. ClioSoft’s VDD< … Read More → "ClioSoft to Introduce Hierarchical Visual Design Diff, Demonstrate Hardware Configuration Management System at DAC 2011"

SAN JOSE, CA – June 1, 2011 — ATopTech, the leader in next generation physical design solutions, will present significant technology additions and performance gains in its Aprisa™ and Apogee™ tools at DAC 2011 in San Diego. Aprisa is the company’s complete place … Read More → "ATopTech Shows Innovations and Performance Gains in Aprisa and Apogee Physical Design Solutions at DAC 2011"