SANTA CLARA, CALIF. –– June 2, 2011 — Oasys Design Systems today announced that its Chip Synthesis™ platform, in use in production environments, now includes design for test (DFT) capabilities, further extending the fast speed and high capacity of Oasys’ RealTime Designer™ software. 

This follows an earlier announcement that the Chip Synthesis platform supports chip-level power analysis and optimization, and has the ability to synthesize a design from the register transfer level (RTL) with UPF … Read More → "Oasys Design Systems adds DFT Capabilities to Chip Synthesis"

WILSONVILLE, Ore., May 31, 2011 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Catapult^® C high-level synthesis tool now supports the synthesis of transaction level models (TLM). TLM synthesis provides the foundation for an executable methodology allowing interplay between Catapult C Synthesis and the Vista™ platform, resulting in a complete TLM 2.0-based solution for virtual prototyping and hardware implementation and enabling the creation of synthesis-ready virtual platforms.

Expanding its full-chip synthesis technology, the Catapult … Read More → "Mentor Graphics Forges TLM Synthesis Link Between Hardware Implementation and Virtual Prototyping"

INTEGRATED ELECTRICAL SOLUTIONS EXPO, Detroit, Mich., June 2, 2011 – Mentor Graphics Corporation (NASDAQ: MENT) announced today a significant expansion of the company’s Capital® product suite. Already offering a powerful electrical system and wire harness design flow for the automotive, aerospace and defence industries, the Capital suite now includes three new products that extend that flow both upstream and downstream. With the introduction of new tools addressing configuration complexity, harness manufacturing and vehicle documentation … Read More → "Mentor Graphics Announces New Capital Tools that Expand Coverage Beyond the Electrical Design Domain"