Louisville, CO – December 8, 2010 – The 2011 Design and Verification Conference (DVCon), sponsored by Accellera, continues its tradition of providing a technical program unparalleled in its industry.  The advance program and registration information is now available on the website (www.dvcon.org). DVCon 2011 will be held February 28-March 3 at the DoubleTree Hotel in San Jose, California.  

The keynote will be presented by Wally Rhines, chairman and CEO of Mentor Graphics, on Tuesday, March 1 at 4:00pm in the Oak/Fir Ballroom.  The industry leaders … Read More → "DVCon 2011 Announces Technical Program"

SAN JOSE, CA and SHANGHAI, CHINA–(Marketwire – December 8, 2010) – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Semiconductor Manufacturing International Corporation (“SMIC”) (NYSE: SMI) (SEHK: 981), the largest semiconductor foundry in China, has adopted Cadence® Silicon Realization products for the design-for-manufacturing (DFM) and low-power technology at the core of SMIC’s 65-nanometer Reference Flow 4.1. Using Cadence Encounter Digital Implementation System as the foundation, the companies collaborated … Read More → "SMIC Adopts Cadence DFM and Low-Power Silicon Realization Technology for 65-Nanometer Reference Flow"

MOUNTAIN VIEW, Calif., Dec. 7, 2010 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate availability of DesignWare® IP for the Mobile Industry Processor Interface (MIPI®) Display Serial Interface (DSI) Host Controller . With this latest addition, Synopsys broadens itsDesignWare MIPI IP portfolio consisting of the Read More → "Synopsys Expands DesignWare MIPI IP Portfolio With DSI Host Controller"

ACTON, MASS. –– December 7, 2010 –– Carbon Design Systems™, a leading supplier of tools for the automatic creation, validation and deployment of system-level models, today announced December 20 availability of implementation-accurate models of the ARM Cortex™-A5 and the ARM Cortex™-M4 processors. 

Models are available through Carbon IP Exchange for designers using SoC Designer Plus.  Carbon IP Exchange is a recently introduced web-based portal with round-the-clock availability where models are generated directly from ARM’s register transfer level (RTL) code using Carbon Model Studio.  Models are constructed … Read More → "Carbon Adds Additional ARM Processor Content to Carbon IP Exchange"

SAN JOSE, Calif., Dec. 7, 2010 – Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, today announced that NetLogic Microsystems Inc. (Nasdaq: NETL), a worldwide leader in high-performance intelligent semiconductor solutions for Internet networks, has selected Talus® for implementation of its next-generation knowledge-based processor and physical layer products. This expands upon the relationship between NetLogic Microsystems and Magma Design Automation, as NetLogic Microsystems has successfully taped out designs in process nodes ranging from 130 to 40 nanometers (nm) using Talus Vortex, Talus Plan Pro and Talus Power Pro. Talus& … Read More → "NetLogic Microsystems Selects Magma’s Talus IC Implementation System for Next-Generation 28-nm Knowledge-based Processor and Physical Layer Products"

THAME, United Kingdom, December 6, 2010 – Imperas™ today released its first models of the Cortex family of processor cores from ARM. Models of the M-series of cores are now available from Open Virtual Platforms™ (OVP™), including example virtual platforms incorporating the cores and support for the cores in Imperas’ advanced software development tools. Additionally, these and other models will be used by Imperas in its collaboration with Cadence Design Systems to deliver on the EDA360 vision for System Realization. 

The processor core models and example platforms are available from the Open Virtual Platforms … Read More → "Imperas and OVP Support ARM Cortex-M Cores and Provide Free, Open Source Models"