News – Page 1576 – EEJournal

Fairchild Semiconductor’s New Motion SPM® 5 Series Offers Thermal Sensing and Stable EMI for Small Home Appliances

July 10, 2013

SAN JOSE, Calif. – July 10, 2013 – Designers of motor control systems need solutions that optimize efficiency and ensure maximum reliability under harsh application conditions. To meet this challenge, Fairchild Semiconductor (NYSE: FCS) developed the SPM^® 5 smart power module series 3-phase MOSFET inverter solution, providing designers an AC induction motor (ACIM) and Brushless DC (BLDC) motor inverter solution for motors up to 200W including fan motors, dish washer pumps, and various small industrial motors.

Cadence Significantly Accelerates Chip Design With New Virtuoso Layout Suite for Electrically Aware Design

July 10, 2013

SAN JOSE, CA–(Marketwired – July 10, 2013) – Cadence Design Systems (NASDAQ: CDNS)

HIGHLIGHTS:Cadence Design Systems (NASDAQ: CDNS)

Cadence Virtuoso Layout Suite Electrically Aware Design (EAD) can save engineers days to weeks of design time by enabling real-time parasitic extraction during layout.
New product and methodology reduces need for multiple design iterations and “over design,” translating to better performance and less area.

Telit Technology to Help Bring Environmental Noise Pollution under Control

July 9, 2013

RALEIGH, N.C. and LONDON – July 9, 2013 – Telit Wireless Solutions, a global provider of high-quality machine-to-machine (M2M) solutions, products and services, today announced collaboration with Poland-based Svantek Sp. z o.o. on development of cellular-connected SV200 noise monitoring station. The Svanteksolution proposes to change the traditional approach of combating noise pollution in populated areas by making prolific environmental noise data collection via cellular connected stations affordable and easy to use. Health and regulatory agencies have largely relied on statistical computer modeling rather than actual data collection to develop work on noise abatement policies and regulatory recommendations. The goal of … Read More → "Telit Technology to Help Bring Environmental Noise Pollution under Control"

CUI Launches High Isolation Dc-Dc Converters with 105oC Operating Temperature Range for Challenging Applications

July 9, 2013

TUALATIN, Ore. – July 9, 2013 – CUI Inc has introduced a family of low-power board mount dc-dc converters that provides 3000 Vdc I/O isolation and an ultra-wide operating temperature range of -40~105°C for the most demanding applications.

The unregulated PEM series is the latest addition to CUI’s second-generation low power dc-dc converter line and has been specifically designed to improve efficiency and thermal performance in the customer’s application. The 1 W / 2 W family offers a rugged and reliable solution for converting and isolating … Read More → "CUI Launches High Isolation Dc-Dc Converters with 105oC Operating Temperature Range for Challenging Applications"

Imec reveals method of damage free cryogenic etching of ultralow-k dielectrics

July 9, 2013

SEMICON WEST, San Francisco (USA) – July 09, 2013 – Imec today announced a cryogenic etching method that protects the surface of porous ultralow-k dielectrics against excessive plasma induced damages.

As semiconductor technology scales below the 20nm node, the capacitance increases between nearby conductive portions of high-density integrated circuits, resulting in loss of speed and cross-talk of the device. To control the increase in capacitance in deeply-scaled devices, insulating layers of porous low-k dielectrics are integrated through plasma etching. However, plasma etching exposes the dielectrics to … Read More → "Imec reveals method of damage free cryogenic etching of ultralow-k dielectrics"

IAR Systems strengthens development tools for Atmel AVR32 with 80 percent faster code and new functionality

July 9, 2013

Uppsala, Sweden—July 9, 2013—Today, IAR Systems® announces the availability of version 4.20 of its embedded development toolchain IAR Embedded Workbench® for AVR32. In addition to user-friendly functionality, the version includes major enhancements to the advanced code optimizations technology, gaining significantly faster code execution as well as smaller code size. The enhancements result in heavily improved scores on the CoreMark® benchmark test suite. Scores are more than 80 percent higher compared to the previous version.

New functionality includes a new text editor with user-friendly features such … Read More → "IAR Systems strengthens development tools for Atmel AVR32 with 80 percent faster code and new functionality"

Fujitsu Laboratories Implements Custom Processor for 3G/LTE Modem with Synopsys’ Processor Designer

July 9, 2013

MOUNTAIN VIEW, Calif., July 9, 2013 /PRNewswire/

Highlights

Synopsys Processor Designer™ tool enables rapid exploration of processor architectures to optimize for performance, power and area
Fujitsu Laboratories created a custom DSP with Processor Designer for multi-mode 3G/LTE modem that delivers higher performance than general purpose DSPs with 20 percent lower power
Software tool chain automatically generated by Processor Designer enables early software development and debugging

Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP … Read More → "Fujitsu Laboratories Implements Custom Processor for 3G/LTE Modem with Synopsys’ Processor Designer"

Leti’s IDEAL and IMAGINE Programs Demonstrate Cost-effective Solutions to Extend 193nm Immersion Lithography for 1X Nodes

July 9, 2013

GRENOBLE, France – July 9, 2013 – CEA-Leti said today that its multi-partner programs, IDEAL and IMAGINE, have demonstrated cost-effective solutions that extend 193nm immersion lithography for 1X nodes for critical levels such as contact and via, and for the cut layer, when multi-patterning is used.

Leti and Arkema launched the IDEAL program in 2011 to develop lithography techniques based on nanostructured polymers, using 300mm directed self-assembly (DSA) process and material solutions for 1X nodes. The partners, which include Sokudo, Tokyo Electron, STMicroelectronics and advanced academic laboratories, such as LTM and LCPO, have demonstrated DSA resolution capability down to sub-10nm half-pitch.</ … Read More → "Leti’s IDEAL and IMAGINE Programs Demonstrate Cost-effective Solutions to Extend 193nm Immersion Lithography for 1X Nodes"

Xilinx Tapes-Out First 20nm All Programmable Device with First UltraScale ASIC-class Programmable Architecture

July 9, 2013

SAN JOSE, Calif., July 9, 2013 – Xilinx, Inc. (NASDAQ: XLNX) announced two more industry firsts at 20nm, expanding on a series of industry innovations started at 28nm. Xilinx has now taped out the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. Xilinx has also implemented the industry’s first ASIC-class programmable architecture called UltraScale™. These milestones expand on Xilinx’s industry first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC-strength design suite.

“With the industry’s most aggressive 20nm tape-out schedule, I believe … Read More → "Xilinx Tapes-Out First 20nm All Programmable Device with First UltraScale ASIC-class Programmable Architecture"

Cadence Solutions Enable Successful Tape Out of 20-Nanometer SoC Test Chip by Global Unichip Corporation

July 9, 2013

SAN JOSE, CA–(Marketwired – July 09, 2013) – Cadence Design Systems (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that the design services company, Global Unichip Corporation (GUC), utilized the Cadence® Encounter® Digital Implementation System (EDI) and Cadence Litho Physical Analyzer to successfully complete the tape out of a 20nm system-on-a-chip (SoC) test chip. Engineers from the two companies collaborated closely using the Cadence solutions to overcome implementation and DFM verification challenges to complete the … Read More → "Cadence Solutions Enable Successful Tape Out of 20-Nanometer SoC Test Chip by Global Unichip Corporation"

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