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VisualSim Architect 10.3 increases engineering productivity using extensive emerging application templates, libraries and shorter simulation times to create accurate visual specifications

Sunnyvale, CA. — October 5, 2010 — Mirabilis Design Inc., a Silicon Valley software provider of system-level modeling and simulation solutions, announces the release of VisualSim Architect 10.3. This release has Model Templates for over 120 applications including multi-core; SoC and avionics power management; Network-on-Chip (NoC); high-performance storage; and real-time software design. Mirabilis Design is also announcing a new infrastructure with user-customizable graphical interface, new modeling components and interactive documentation.

Our user community has already realized massive productivity improvements from this release. The new NoC Template was used by a large Wireless Semiconductor company to model a Gigahertz-range multimedia SoC in approximately three … Read More → "VisualSim Architect 10.3 increases engineering productivity using extensive emerging application templates, libraries and shorter simulation times to create accurate visual specifications"

Synopsys Acquires Optical Research Associates

MOUNTAIN VIEW, Calif., Oct. 7 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, has acquired Optical Research Associates (ORA®), a privately held leading provider of optical design software and optical engineering services. The addition of ORA’s expertise, technology and products will allow Synopsys to move into the rapidly growing markets associated with displays and solid state lighting using light emitting diodes (LEDs), as well as expand into markets such as semiconductor lithography equipment and cameras. This acquisition represents Synopsys’ initial move into this space and aligns with the … Read More → "Synopsys Acquires Optical Research Associates"

austriamicrosystems introduces “More Than Silicon” initiative

Unterpremstaetten, Austria (October 7, 2010) – austriamicrosystems Full Service Foundry business unit today introduced its “More Than Silicon” initiative, a comprehensive service and technology package that goes beyond industry standard foundry services. Foundry customers instantly benefit from access to leading edge technology add-ons, advanced packaging services and dedicated support engineers to enable first-time-right designs.

The “More Than Silicon” offering provides austriamicrosystems’ foundry customers access to leading edge 3D-IC integration using austriamicrosystems’ patented Through Silicon Via technology ( … Read More → "austriamicrosystems introduces “More Than Silicon” initiative"

Agilent Technologies Continues Expansion of Source Measure Unit Offering with New 4-Quadrant General Purpose Model

SANTA CLARA, Calif., Oct. 4, 2010 — Agilent Technologies Inc. (NYSE: A) today announced the N6784A 4-quadrant general-purpose source measure unit (SMU), the newest member of the N6700 Modular Power System family. The N6784A SMU offers advanced sourcing and measurement capabilities in four quadrants, required for many general-purpose electronic test applications.

“General-purpose applications span a large number of industries with vastly different test requirements,” said Gary Whitman, vice president … Read More → "Agilent Technologies Continues Expansion of Source Measure Unit Offering with New 4-Quadrant General Purpose Model"

austriamicrosystems announces best-in-class 3-channel low-frequency wake-up receiver with 15 – 150kHz range & automatic antenna tuning capability

Unterpremstaetten, Austria (October 6, 2010) – austriamicrosystems (SIX: AMS), a leading global designer and manufacturer of high-performance analog ICs introduces the AS3933, a 3-channel low-frequency wake-up receiver that enables battery powered systems to add remote wakeup capability. In addition, with best-in-class sensitivity of 80 µVrms, both range and BOM cost can be optimized while the lowest current consumption of 2.7 μA extends battery life.

Featuring a wide receive frequency range — 15 to 150 kHz — the AS3933 offers flexibility to designers for a … Read More → "austriamicrosystems announces best-in-class 3-channel low-frequency wake-up receiver with 15 – 150kHz range & automatic antenna tuning capability"

Deutschmann Automation selects Innovasic Semiconductor’s RapID™ Platform for their ProfiNET Connectivity Solution

Albuquerque, New Mexico, October 2010 – Deutschmann Automation and Innovasic Semiconductor are pleased to announce that Deutschmann has incorporated Innovasic’s RapID Platform and fido1100®Communications Controller into their UNIGATE® IC and UNIGATE® CL Profinet gateway products. The UNIGATE CL is a protocol converter solution for all field devices with serial interfaces.  The UNIGATE IC is a protocol converter that supports integration directly into industrial automation equipment. Innovasic’s RapID Platform solution provides the communication processing in these gateway … Read More → "Deutschmann Automation selects Innovasic Semiconductor’s RapID™ Platform for their ProfiNET Connectivity Solution"

Spectrum Digital Announces New JTAG Emulator

Kane Computing Ltd (KCL) are pleased to announce that Spectrum Digital Inc. the leading provider of development tools for Texas Instruments (TI) Digital Signal Processors (DSPs), announces the introduction of the XDS560v2 System Trace JTAG Emulator for single chip DSPs, multi-core devices, and SoCs produced by Texas Instruments.

This new emulator delivers a higher level of debug capability required by the developer using these high performance processors. These new capabilities are aimed at developing better software, reducing the development cycle, and shortening time to market. The emulator offers standard features not previously available in the TI … Read More → "Spectrum Digital Announces New JTAG Emulator"

TSMC Expands IP Alliance to Include Soft IP

HSINCHU, Taiwan, R.O.C., Oct. 5 — TSMC (TWSE: 2330, NYSE: TSM) today expanded its IP Alliance to incorporate a soft IP program that will improve soft IP readiness for advanced technology nodes and drive earlier time-to-market.

TSMC is expected to provide specific design documents and technology information  through the program so that partners can optimize their soft IP to TSMC’s technology. TSMC will also collaborate with these companies to expedite soft IP readiness by aligning their development with TSMC’s process technology roadmap.

Soft IP has historically been process technology independent and therefore was … Read More → "TSMC Expands IP Alliance to Include Soft IP"

GN ReSound Standardizes on Magma Talus to Increase Performance and Minimize Power on Next-Generation ICs

SAN JOSE, Calif., Oct. 5, 2010 — Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, today announced that GN ReSound, a world leader in innovative hearing instruments, has standardized on the Talus® implementation system for its next-generation ICs. GN ReSound selected Talus after encountering difficulty closing timing while meeting low-power requirements on a critical design with its previous tools. Talus delivered a fast, predictable and repeatable flow that allowed GN ReSound to quickly perform trial place-and-route runs to find the optimal power/performance tradeoff. 

Read More → "GN ReSound Standardizes on Magma Talus to Increase Performance and Minimize Power on Next-Generation ICs"

CEA-Leti Makes a R&D 20nm Fully Depleted SOI Process available through CMP

Grenoble, FRANCE, and Tokyo, JAPAN, October 1st, 2010, CEA-Leti and CMP (Circuits Multi Projets®) announced during the FDSOI Workshop at Tokyo Universitythe launch of an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process, opening the access of its 300mm infrastructure to the design community. This MPW offer is partly supported by EUROSOI+ network that gathers the main European academic partners on SOI.

“The Leti has pioneered the SOI technology for years, leading track records in the most advanced research in FDSOI, assessing its … Read More → "CEA-Leti Makes a R&D 20nm Fully Depleted SOI Process available through CMP"

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